Patents by Inventor William R. Harshbarger

William R. Harshbarger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6352910
    Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: March 5, 2002
    Assignee: Applied Komatsu Technology, Inc.
    Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law
  • Patent number: 6200651
    Abstract: A dielectric layer is deposited on a workpiece by a chemical vapor deposition method in an electron cyclotron resonance vacuum plasma processor having a plasma chamber responsive to a repetitively pulsed microwave field and gases from a plasma source. A reaction chamber responds to at least one reacting gas containing at least one element that chemically reacts in the presence of the plasma with at least one element in at least one of the gases from the plasma source to form the deposited layer on the workpiece. The turn off periods are long enough to cause electrons in the plasma on the deposited dielectric layer to be cooled sufficiently (from about 3.5 eV to a lower value having a minimum value of about 0.1 eV) to reduce the tendencies for opposite polarity charges to be established across the deposited dielectric layer and for damaging discharge current to flow across the deposited dielectric layer.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 13, 2001
    Assignee: Lam Research Corporation
    Inventors: Gregory A. Roche, William R. Harshbarger
  • Patent number: 4208241
    Abstract: High density fine-line integrated structure fabrication is expedited by use of plasma etching systems which assure straight vertical walls (absence of undercutting). Critical to the sytems is choice of appropriate plasma chemistry. Appropriate systems are characterized by inclusion of recombination centers, as well as active etchant species. Recombination centers which effectively terminate etchant species lifetime in the immediate vicinity of resist walls afford means for controlling etching anisotropy. Use is foreseen in large scale integrated circuitry (LSI) and is expected to be of particular interest for extremely fine design rules, i.e., in Very Large Scale Integrated circuitry.
    Type: Grant
    Filed: July 31, 1978
    Date of Patent: June 17, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: William R. Harshbarger, Hyman J. Levinstein, Cyril J. Mogab, Roy A. Porter
  • Patent number: 4181564
    Abstract: A method of forming patterned insulating layers such as silicon nitride for use in integrated circuit fabrication is disclosed. The insulating layer is formed by reactive plasma deposition while the temperature of the substrate is decreased. This diminishing temperature affects the etching characteristics of the layer such that when openings are formed by a selective plasma etching, the sidewalls will be sloped at an acute angle with the substrate even when the layer is overetched.
    Type: Grant
    Filed: April 24, 1978
    Date of Patent: January 1, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Thomas N. Fogarty, William R. Harshbarger, Roy A. Porter