Abstract: A structure and associated method for protecting an electrical structure during a fuse link deletion by focused radiation. The structure comprises a fuse element, a protection plate, a first dielectric layer, and a second dielectric layer. The structure is formed within a semiconductor device. The protection plate is formed within the first dielectric layer using a damascene process. The second dielectric layer is formed over the protection plate and the first dielectric layer. The fuse element is formed over the second dielectric layer. The fuse element is adapted to be cut with a laser beam. The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The protection plate is adapted to shield the first dielectric layer from energy from the laser beam.

Abstract: The act of blowing an unpassivated electrical fuse (for example, fuse 405) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier 406) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in/stress. Also provided is a method for implementing the wafer level product burn-in/screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system. Pursuant to a preferred aspect all chips of a wafer are stressed simultaneously without having a probe physically contact any chip during the stress procedure. This concept can be applied to burn-in of product wafers, voltage screen of product wafers, and reliability evaluations of various failure mechanisms.

Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low &kgr; nanopore/nanofoam dielectric material adjacent the conductive line ends.

Abstract: A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc.

Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: A laser alignment target is provided having a surface that is out of plane with and has substantially the same first reflectivity as an adjacent surface of the semiconductor device, and a sidewall having a second reflectivity different than the first reflectivity. The target provides sidewalls that provide contrast for finding the target despite loss of contrast created by layers of dielectric over the target and use of short wavelength light.

Abstract: A semiconductor device having at least one fuse and an alignment mark formed therein. An etch resistant layer over the surface of the fuse and alignment mark, which provides a uniform passivation thickness for use in conjunction with laser fuse deletion processes.

Abstract: A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.

Abstract: The present invention relates to dissipating heat from an interconnect formed in a low thermal conductivity dielectric in an integrated circuit apparatus. The integrated circuit apparatus includes integrated circuit devices interconnected by conductive interconnection metallurgy and input/output pads subject to electrostatic discharge events. At least one latent heat of transformation absorber is associated with at least one of the input/output pads for preventing the energy generated by an electrostatic discharge event from damaging the conductive interconnection metallurgy.

Abstract: A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in/stress. Also provided is a method for implementing the wafer level product burn-in/screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system. Pursuant to a preferred aspect all chips of a wafer are stressed simultaneously without having a probe physically contact any chip during the stress procedure. This concept can be applied to burn-in of product wafers, voltage screen of product wafers, and reliability evaluations of various failure mechanisms.

Abstract: A semiconductor device having at least one fuse and an alignment mark formed therein. An etch resistant layer over the surface of the fuse and alignment mark, which provides a uniform passivation thickness for use in conjunction with laser fuse deletion processes.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.

Abstract: A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.