Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in/stress. Also provided is a method for implementing the wafer level product burn-in/screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system. Pursuant to a preferred aspect all chips of a wafer are stressed simultaneously without having a probe physically contact any chip during the stress procedure. This concept can be applied to burn-in of product wafers, voltage screen of product wafers, and reliability evaluations of various failure mechanisms.

Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable.

Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable. The magnetic device can be programmed into one of three magnetic field orentations or states. Conventional VLSI fabrication steps are used for compatability with low-k dielectric Back-End-Of-Line (BEOL) processing.

Abstract: A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.

Abstract: A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Abstract: A thermal management system for a semiconductor chip including at least one region of thermally conductive material included internally within the semiconductor chip.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Abstract: A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially- similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A metallization composite comprises a refractory metal, nickel, and copper. The refractory metal is preferably titanium (Ti), but other suitable refractory metals such as zirconium and hafnium can also be utilized. An additional optional layer of gold can overlie the copper. The metallization composite is used to connect a solder contact to a semiconductor substrate.

Abstract: A polyamic acid copolymer forming a polyimide comprising, in mole percent, from greater than 5 percent to about 45 percent pyromellitic dianhydride, from about 5 percent to about 45 percent oxydiphthalic dianhydride, and about 50 percent of oxydianiline. Polyimides formed by curing the copolymer are also disclosed as is a process for forming a heat sealable coating on or dielectric isolation layer within electronic circuitry using the copolymer.