Patents by Inventor William Thie

William Thie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230223292
    Abstract: In some examples, a flat Bottom Shadow Ring (fBSR) is provided for processing a substrate in a processing chamber. An example fBSR comprises an overhang for covering an edge of the substrate in the processing chamber. The overhang includes a fiat zone that extends radially outward over the outer edge of the substrate.
    Type: Application
    Filed: June 10, 2021
    Publication date: July 13, 2023
    Inventors: Lai Wei, Ji Soo Kim, Alan Jeffrey Miller, William Thie, Frank Yun Lin, Jun Hee Hee Han, Jie Liu, Conan Chiang, Michael John Martin
  • Publication number: 20220108875
    Abstract: A gas delivery system configured to provide deposition and etch gases to a processing chamber for a rapid alternating process includes a first valve arranged to provide deposition gas from a deposition gas manifold to a first zone of a gas distribution device via a first orifice and provide the deposition gas from the deposition gas manifold to a second zone of the gas distribution device via a second orifice having a diameters than the first orifice. A second valve is arranged to provide etch gas from the etch gas manifold to the first zone of the gas distribution device via a third orifice and provide the etch gas from the etch gas manifold to the second zone of the gas distribution device via a fourth orifice having a different diameter than the third orifice.
    Type: Application
    Filed: January 23, 2020
    Publication date: April 7, 2022
    Inventors: William THIE, Jisoo KIM, Alan J. MILLER, Lai WEl, Frank Y. LIN, Jun Hee Hee HAN, Jie LIU, Conan CHlANG, Michael John MARTIN, Nicholas John CELESTE
  • Patent number: 9997364
    Abstract: A method for etching a layer in a processing chamber is provided. A plurality of cycles is provided, where each cycle comprises a deposition phase, a clearing phase, and an etching phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon or hydrofluorocarbon gas into the processing chamber, maintaining a deposition phase pressure of at least 50 mTorr, transforming the deposition gas into a plasma, and stopping the deposition phase. The clearing phase comprises flowing a clearing gas comprising a halogen containing gas into the processing chamber, maintaining a clearing phase pressure of less than 40 mTorr, transforming the clearing gas into a plasma, and stopping the clearing phase. The etching phase comprises flowing an etching gas comprising a halogen containing gas into the processing chamber, maintaining an etching phase pressure of at least 30 mTorr, transforming the etching gas into a plasma, and stopping the etching phase.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: William Thie, Jisoo Kim
  • Publication number: 20180108531
    Abstract: A method for etching a layer in a processing chamber is provided. A plurality of cycles is provided, where each cycle comprises a deposition phase, a clearing phase, and an etching phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon or hydrofluorocarbon gas into the processing chamber, maintaining a deposition phase pressure of at least 50 mTorr, transforming the deposition gas into a plasma, and stopping the deposition phase. The clearing phase comprises flowing a clearing gas comprising a halogen containing gas into the processing chamber, maintaining a clearing phase pressure of less than 40 mTorr, transforming the clearing gas into a plasma, and stopping the clearing phase. The etching phase comprises flowing an etching gas comprising a halogen containing gas into the processing chamber, maintaining an etching phase pressure of at least 30 mTorr, transforming the etching gas into a plasma, and stopping the etching phase.
    Type: Application
    Filed: October 19, 2016
    Publication date: April 19, 2018
    Inventors: William THIE, Jisoo KIM
  • Patent number: 9287110
    Abstract: A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 15, 2016
    Assignee: Lam Research Corporation
    Inventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
  • Patent number: 9117860
    Abstract: A cluster architecture and methods for processing a substrate are disclosed. The cluster architecture includes a lab-ambient controlled transfer module that is coupled to one or more wet substrate processing modules. The lab-ambient controlled transfer module and the one or more wet substrate processing modules are configured to manage a first ambient environment. A vacuum transfer module that is coupled to the lab-ambient controlled transfer module and one or more plasma processing modules is also provided. The vacuum transfer module and the one or more plasma processing modules are configured to manage a second ambient environment. And, a controlled ambient transfer module that is coupled to the vacuum transfer module and one or more ambient processing modules is also included. The controlled ambient transfer module and the one or more ambient processing modules are configured to manage a third ambient environment.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: August 25, 2015
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Yezdi Dordi, Tiruchirapalli Arunagiri, Benjamin W. Mooring, John Parks, William Thie, Fritz C. Redeker, Arthur M. Howald, Alan Schoepp, David Hemker, Carl Woods, Hyungsuk Alexander Yoon, Aleksander Owczarz
  • Publication number: 20150214093
    Abstract: A method for processing an interconnect structure on a substrate is provided, including: depositing a metallic barrier layer to line the interconnect structure, the metallic barrier layer configured to prevent diffusion of copper into the dielectric layer; depositing a thin copper seed layer over the metallic barrier layer in the interconnect structure; depositing a gap-fill copper layer over the thin copper seed layer; removing copper overburden and metallic barrier overburden, wherein removing copper overburden and metallic barrier overburden creates a planarized copper surface on the gap-fill copper layer; selectively depositing a thin layer of a cobalt-containing material on the reduced planarized copper surface; wherein the substrate is processed and transferred in controlled environments to minimize exposure to oxygen, the controlled environments defined by one or more controlled ambient environments and/or one or more vacuum environments.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 30, 2015
    Inventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Fritz C. Redeker, William Thie, Arthur M. Howald
  • Publication number: 20150034589
    Abstract: A method for forming copper on a substrate including inputting a copper source solution into a mixer, inputting a reducing solution into the mixer, mixing copper source solution and the reducing solution to form a plating solution having a pH of greater than about 6.5 and applying the plating solution to a substrate, the substrate including a catalytic layer wherein applying the plating solution to the substrate includes forming a catalytic layer, maintaining the catalytic layer in a controlled environment and forming copper on the catalytic layer. A system for forming copper structures is also disclosed.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: Alan Lee, Yunsang Kim, Andrew Bailey, III, Yezdi Dordi, William Thie
  • Patent number: 8883027
    Abstract: A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: November 11, 2014
    Assignee: Lam Research Corporation
    Inventors: Hyungsuk Alexander Yoon, William Thie, Yezdi Dordi, Andrew D. Bailey, III
  • Publication number: 20140322446
    Abstract: An integrated system for transferring and processing a substrate in a controlled environment to enable selective deposition of a thin layer of a cobalt-alloy material on a copper surface of a copper interconnect to improve electromigration performance of the copper interconnect, comprising: a lab-ambient transfer chamber; a substrate cleaning reactor coupled to the lab-ambient transfer chamber, wherein the substrate cleaning reactor cleans the substrate surface to remove metal-organic complex contaminants on the substrate surface; a vacuum transfer chamber; a vacuum process module for removing organic contaminants from the substrate surface; a controlled-ambient transfer chamber filled with an inert gas; and an electroless cobalt-alloy material deposition process module used to deposit the thin layer of cobalt-alloy material on the copper surface of the copper interconnect after the substrate surface has been removed of metallic contaminants and organic contaminants, and the copper surface has been removed of
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Fritz C. Redeker, William Thie, Arthur M. Howald
  • Patent number: 8844461
    Abstract: A chemical fluid handling system is defined to supply a number of chemicals to a number of fluid inputs of a mixing manifold. The chemical fluid handling system includes a number of fluid recirculation loops for separately pre-conditioning and controlling the supply of each of the number of chemicals. Each of the fluid recirculation loops is defined to degas, heat, and filter a particular one of the number of chemical components. The mixing manifold is defined to mix the number of chemicals to form the electroless plating solution. The mixing manifold includes a fluid output connected to a supply line. The supply line is connected to supply the electroless plating solution to a fluid bowl within an electroless plating chamber.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: September 30, 2014
    Assignee: Lam Research Corporation
    Inventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
  • Patent number: 8790465
    Abstract: One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: July 29, 2014
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Shijian Li, Tiruchirapalli Arunagiri, William Thie
  • Patent number: 8771804
    Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically copper-to-cobalt-alloy interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a thin layer of a cobalt-alloy material on a copper surface of a copper interconnect of the substrate in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes removing contaminants and metal oxides from the substrate surface in the integrated system, and reconditioning the substrate surface using a reducing environment after removing contaminants and metal oxides in the integrated system.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 8, 2014
    Assignee: Lam Research Corporation
    Inventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Fritz C. Redeker, William Thie, Arthur M. Howald
  • Patent number: 8747960
    Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve silicon-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce a silicon-to-metal interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a layer of a metal on a silicon or polysilicon surface of the substrate to form a metal silicide in an integrated system is provided.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: June 10, 2014
    Assignee: Lam Research Corporation
    Inventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Johan Vertommen, Fritz C. Redeker, William Thie, Arthur M. Howald
  • Patent number: 8691698
    Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 8, 2014
    Assignee: Lam Research Corporation
    Inventors: Qing Xu, William Thie, Camelia Rusu
  • Patent number: 8622020
    Abstract: An electroless plating system is provided. The system includes a first vacuum chuck supporting a first wafer and a second vacuum chuck supporting a second wafer such that a top surface of the second wafer is opposing a top surface of the first wafer. The system also includes a fluid delivery system configured to deliver a plating solution to the top surface of the first wafer, wherein in response to delivery of the plating solution, the top surface of the second wafer is brought proximate to the top surface of the first wafer so that the plating solution contacts both top surfaces. A method for applying an electroless plating solution to a substrate is also provided.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: January 7, 2014
    Assignee: Lam Research Corporation
    Inventors: William Thie, John M. Boyd, Yezdi Dordi, Fritz C. Redeker
  • Patent number: 8603913
    Abstract: A method for forming semiconductor devices on a substrate under a porous low-k dielectric layer, wherein features are formed in the porous low-k dielectric layer and wherein a barrier layer is formed over the porous low-k dielectric layer is provided. Contacts are formed in the features. The barrier layer is planarized. A cap layer is formed over the contacts, wherein the forming the cap layer provides metal and organic contaminants in the porous low-k dielectric layer. The metal contaminants are removed from the porous low-k dielectric layer with a first wet process. The organic components are removed from the porous low-k dielectric layer with a second wet process.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 10, 2013
    Assignee: Lam Research Corporation
    Inventors: Nanhai Li, William Thie, Novy Tjokro, Yaxin Wang, Artur Kolics
  • Publication number: 20130280917
    Abstract: A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.
    Type: Application
    Filed: June 14, 2013
    Publication date: October 24, 2013
    Inventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
  • Publication number: 20130203256
    Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Qing Xu, William Thie, Camelia Rusu
  • Patent number: 8490573
    Abstract: Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: July 23, 2013
    Assignee: Lam Research Corporation
    Inventors: Yezdi Dordi, John Boyd, William Thie, Bob Maraschin, Fred C. Redeker, Joel M. Cook