Patents by Inventor William Thie
William Thie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8485120Abstract: A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.Type: GrantFiled: April 16, 2007Date of Patent: July 16, 2013Assignee: Lam Research CorporationInventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
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Patent number: 8404626Abstract: One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.Type: GrantFiled: December 13, 2008Date of Patent: March 26, 2013Assignee: Lam Research CorporationInventors: Artur Kolics, Shijian Li, Tiruchirapalli Arunagiri, William Thie
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Patent number: 8314027Abstract: A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).Type: GrantFiled: October 28, 2011Date of Patent: November 20, 2012Assignee: Lam Research CorporationInventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
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Publication number: 20120269987Abstract: An integrated system for processing a substrate in controlled environment to enable deposition of a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect is provided. The system includes a lab-ambient transfer chamber, a vacuum transfer chamber, a vacuum process module for cleaning an exposed surface of a metal oxide of a underlying metal, a vacuum process module for depositing the metallic barrier layer, and a controlled-ambient transfer chamber filled with an inert gas, wherein at least one controlled-ambient process module is coupled to the controlled-ambient transfer chamber. In addition, the system includes an electroless copper deposition process module used to deposit the thin layer of copper seed layer on the surface of the metallic barrier layer.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: Lam Research CorporationInventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Hyungsuk Alexander Yoon, Fritz C. Redeker, William Thie, Arthur M. Howald
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Patent number: 8241701Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect.Type: GrantFiled: August 30, 2006Date of Patent: August 14, 2012Assignee: Lam Research CorporationInventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Hyungsuk Alexander Yoon, Fritz C. Redeker, William Thie, Arthur M. Howald
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Patent number: 8133812Abstract: This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization.Type: GrantFiled: September 18, 2009Date of Patent: March 13, 2012Assignee: Lam Research CorporationInventors: Yezdi Dordi, John Boyd, Fritz Redeker, William Thie, Tiruchirapalli Arunagiri, Alex Yoon
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Publication number: 20120045897Abstract: A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).Type: ApplicationFiled: October 28, 2011Publication date: February 23, 2012Applicant: Lam Research CorporationInventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
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Publication number: 20110306203Abstract: An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.Type: ApplicationFiled: August 25, 2011Publication date: December 15, 2011Applicant: Lam Research CorporationInventors: Yezdi Dordi, John M. Boyd, Fritz C. Redeker, William Thie, Tiruchirapalli Arunagiri, Hyungsuk Alexander Yoon
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Patent number: 8069813Abstract: A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).Type: GrantFiled: April 16, 2007Date of Patent: December 6, 2011Assignee: Lam Research CorporationInventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
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Patent number: 8026605Abstract: An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.Type: GrantFiled: December 14, 2006Date of Patent: September 27, 2011Assignee: Lam Research CorporationInventors: Yezdi Dordi, John M. Boyd, Fritz C. Redeker, William Thie, Tiruchirapalli Arunagiri, Hyungsuk Alexander Yoon
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Publication number: 20110081779Abstract: Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.Type: ApplicationFiled: December 14, 2010Publication date: April 7, 2011Applicant: Lam Research CorporationInventors: Yezdi Dordi, John Boyd, William Thie, Bob Maraschin, Fred C. Redeker, Joel M. Cook
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Patent number: 7909934Abstract: A system and method of cleaning a substrate includes a megasonic chamber that includes a transducer and a substrate. The transducer is being oriented toward the substrate. A variable distance d separates the transducer and the substrate. The system also includes a dynamically adjustable RF generator that has an output coupled to the transducer.Type: GrantFiled: August 31, 2005Date of Patent: March 22, 2011Assignee: Lam Research CorporationInventors: John Boyd, Andras Kuthi, Michael G. R. Smith, Thomas W. Anderson, William Thie
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Patent number: 7884017Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.Type: GrantFiled: February 3, 2010Date of Patent: February 8, 2011Assignee: Lam Research CorporationInventors: Zhonghui Alex Wang, Tiruchirapalli Arunagiri, Fritz C. Redeker, Yezdi Dordi, John Boyd, Mikhail Korolik, Arthur M. Howald, William Thie, Praveen Nalla
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Patent number: 7875554Abstract: Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.Type: GrantFiled: March 7, 2008Date of Patent: January 25, 2011Assignee: Lam Research CorporationInventors: Yezdi Dordi, John Boyd, William Thie, Bob Maraschin, Fred C. Redeker, Joel M. Cook
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Publication number: 20110011335Abstract: An electroless plating system is provided. The system includes a first vacuum chuck supporting a first wafer and a second vacuum chuck supporting a second wafer such that a top surface of the second wafer is opposing a top surface of the first wafer. The system also includes a fluid delivery system configured to deliver a plating solution to the top surface of the first wafer, wherein in response to delivery of the plating solution, the top surface of the second wafer is brought proximate to the top surface of the first wafer so that the plating solution contacts both top surfaces. A method for applying an electroless plating solution to a substrate is also provided.Type: ApplicationFiled: September 27, 2010Publication date: January 20, 2011Inventors: William Thie, John M. Boyd, Yezdi Dordi, Fritz C. Redeker
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Patent number: 7829152Abstract: An electroless plating system is provided. The system includes a first vacuum chuck supporting a first wafer and a second vacuum chuck supporting a second wafer such that a top surface of the second wafer is opposing a top surface of the first wafer. The system also includes a fluid delivery system configured to deliver a plating solution to the top surface of the first wafer, wherein in response to delivery of the plating solution, the top surface of the second wafer is brought proximate to the top surface of the first wafer so that the plating solution contacts both top surfaces. A method for applying an electroless plating solution to a substrate is also provided.Type: GrantFiled: October 5, 2006Date of Patent: November 9, 2010Assignee: Lam Research CorporationInventors: William Thie, John M. Boyd, Yezdi Dordi, Fritz C. Redeker
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Publication number: 20100239767Abstract: An electroless plating chamber is provided. The electroless plating chamber includes a chuck configured to support a substrate and a bowl surrounding a base and a sidewall of the chuck. The base has an annular channel defined along an inner diameter of the base. The chamber includes a drain connected to the annular channel. The drain is capable of removing fluid collected from the chuck. A proximity head capable of cleaning and substantially drying the substrate is included in the chamber. A method for performing an electroless plating operation is also provided.Type: ApplicationFiled: May 28, 2010Publication date: September 23, 2010Inventors: Yezdi Dordi, William Thie, John M. Boyd, Fritz C. Redeker, Aleksander Owczarz
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Patent number: 7752996Abstract: An electroless plating chamber is provided. The electroless plating chamber includes a chuck configured to support a substrate and a bowl surrounding a base and a sidewall of the chuck. The base has an annular channel defined along an inner diameter of the base. The chamber includes a drain connected to the annular channel. The drain is capable of removing fluid collected from the chuck. A proximity head capable of cleaning and substantially drying the substrate is included in the chamber. A method for performing an electroless plating operation is also provided.Type: GrantFiled: December 15, 2006Date of Patent: July 13, 2010Assignee: Lam Research CorporationInventors: Yezdi Dordi, William Thie, John M. Boyd, Fritz C. Redeker, Aleksander Owczarz
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Publication number: 20100136788Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.Type: ApplicationFiled: February 3, 2010Publication date: June 3, 2010Applicant: Lam Research CorporationInventors: Zhonghui Alex Wang, Tiruchirapalli Arunagiri, Fritz C. Redeker, Yezdi Dordi, John Boyd, Mikhail Korolik, Arthur M. Howald, William Thie, Praveen Nalla
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Publication number: 20100108491Abstract: A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Inventors: Hyungsuk Alexander Yoon, William Thie, Yezdi Dordi, Andrew D. Bailey, III