Abstract: A method and apparatus to establish independence between nodes in a distributed network during protection switching. A translation module that may include a cross connect table is introduced onto a backplane of a line card between a switch fabric and an egress time slot interchange (ETSI) module. Logical identifiers are assigned to the inputs of the ETSI module during system initialization. After initialization, the logical identifiers remain fixed. The translation module maps physical identifiers for incoming signals to the logical identifiers. If a line outage occurs, the translation module remaps the physical identifier for the protection line to the logical identifier corresponding to the failed line.

Abstract: A platform-independent process for data retrieval from ontology-oriented data systems over computer networks through a flexible system and method of query paraphrasing. The present invention uses a “common ontology” that is not tied to any particular data system. Thus, each client computer issues queries to a target data system in the common ontology. Of course, the target data system will not be able to directly process the query (as it is not in its local ontology). Instead, the query is first paraphrased back from the common ontology into local ontology by taking the semantic query, passing it through a query paraphraser, and then sending the paraphrased query to the data system. Once it is paraphrased successfully, the target data system can process it and produce a result using local ontology. The result may then be sent from the data system to an answer paraphraser for paraphrasing, and the paraphrased answer may be returned to its original query issuer and on to the client.

Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture.

Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

Abstract: A system for communication on a chip. The system includes an on-chip communication bus including plural tracks, and a plurality of stations that couple a plurality of on-chip components to the on-chip communication bus, whereby the plurality of on-chip components use the tracks to communicate. Each station preferably includes an initiator that requests permission to transmit outgoing data over a track to another station and that transmits the outgoing data, an arbiter that evaluates requests from other stations and selects a track on which to receive incoming data, and a target that receives the incoming data. The initiator can be connected to a grant multiplexor for selecting a grant line, with the grant multiplexor further including plural smaller multiplexors distributed across the chip. Likewise, the arbiter can be connected to a track multiplexor for selecting a track, with the track multiplexor further including plural smaller multiplexors distributed across the chip.

Abstract: A flexible shaft coupling sleeve comprising a sleeve shaped body having a central annular portion and a coupling receiving portion at each of two opposing sleeve ends, and a coupling device incorporating such sleeve. The sleeve's coupling receiving portions include axially extending teeth on their inner surfaces. The flexible shaft coupling sleeve is formed of a polyurethane elastomer composition.

Abstract: A method and system for facilitating merchant-initiated online payments are disclosed. According to one aspect of the present invention, a payment service provider's server receives a user's request, via a merchant's server, to establish a merchant-initiated payment relationship or agreement. Accordingly, the payment service provider presents the user with options to customize the terms of the merchant-initiated payment agreement. After the agreement has been established and the terms customized, the merchant server communicates a merchant-initiated payment request to the pavement service provider for a transaction entered into with the user. The payment service provider's server processes the payment request after verifying that processing the payment does not exceed the user-customized terms of the agreement.

Abstract: The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.

Abstract: The present invention is a general method for inactivating or inhibiting ribonucleases. Ribonucleases are treated with a reducing agent and heat. RNA samples contaminated with ribonuclease may be treated with this method to protect them from degradation. The RNA may then be used directly in a variety of enzymatic reactions and molecular biology techniques. This method may also be applied to a variety of molecular biology reagents which may be contaminated with ribonuclease to protect an RNA from being degraded when incubated with the reagent.

Abstract: A laminated edible product having a plurality of thin extruded layers, which include at least one fluid first material interleaved between a second fluid material. The extruded layers are superimposed on top of one another in an oscillating arrangement such that the product has a thickness from about 0.01 inches to 4 inches.

Abstract: The present invention is a general method for irreversibly inactivating ribonucleases. Ribonucleases are completely inactivated by treating them with a reducing agent and heat. RNA samples contaminated with ribonuclease may be treated with this method to protect them from degradation. The RNA may then be used directly in a variety of enzymatic reactions and molecular biology techniques. This method may also be applied to a variety of molecular biology reagents which may be contaminated with ribonuclease to protect an RNA from being degraded when incubated with the reagent.

Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture.

Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit.

Abstract: A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a lesser number of banks. To accomplish this, a control (bit) is produced on the chip Mode Register Set (MRS) that activates corresponding logic in the chip to move one of the bits used to address a memory cell, such as one of the row address bits, to a position of the bank ID field. This provides a greater number of bank ID bits to select memory banks of a chip so that a high number bank chip can accept a command supplied by a controller designed to operate a chip with a fewer number of banks and that has a format of a lesser number of bank ID bits.

Abstract: The invention relates to an apparatus for producing a laminated edible product such as a candy product. This apparatus includes a support capable of movement; a coaxial die assembly for depositing one or more layers of a fluid material onto the support; a die holder, for supporting the coaxial die assembly and being positioned above the support; and one or more drive assemblies for providing oscillating movement between the coaxial die and the support.

Abstract: A pin has a front side having a recess therein and a back side having a connector for attaching the pin to an article of clothing. The recess is capable of having a photograph attached therein. The pin provides users of pins with flexibility in designing pins to personal taste. In another version the pin has two hinged sections that can be opened and closed like a book, with each section having a recess for a photo.

Abstract: Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.

Abstract: The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.

Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.

Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.