Abstract: Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.

Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array.

Abstract: The present invention is a general method for inactivating or inhibiting ribonucleases. Ribonucleases are treated with a reducing agent and heat. RNA samples contaminated with ribonuclease may be treated with this method to protect them from degradation. The RNA may then be used directly in a variety of enzymatic reactions and molecular biology techniques. This method may also be applied to a variety of molecular biology reagents which may be contaminated with ribonuclease to protect an RNA from being degraded when incubated with the reagent.

Abstract: The inventive third-axis input device is integrally formed and arranged between two racks on the mouse base, which have a predetermined distance therebetween. The third-axis input device comprises a roller, two shafts each extending from lateral side of the roller and arranged on the rack, an encode wheel formed integrally on the first shaft and placed within an IR module of the mouse, the second shaft is corresponding to a micro switch. An abutting wheel is formed integrally with the first shaft and has a plurality of dents and bumps on the rim thereof and having a predetermined separation. A supporting member with elastic displacement is arranged on the base and corresponding to the abutting wheel. The abutting wheel is pushed by the supporting member when the user rotates the roller. The user can feel the lifting and falling movement of the roller and has better feeling for coordinate movement.

Abstract: The invention relates to a method and apparatus for producing a laminated edible product such as a candy product. This method includes the steps of extruding from the exit port of a coaxial die a thin strip of a first fluid material encased in a layer of a second fluid material, depositing the thin strip on a support, and superimposing additional thin strip on top of the first thin strip. The invention also relates to an edible product prepared by this method.

Abstract: A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.

Abstract: A computer system having central processors (CPs), an associated L2 cache, and processor memory arrays (PMAs), is provided with store logic and and fetch logic used to detect and correct data errors and to write the resulting data the associated cache. The store logic and and fetch logic blocks UEs from the cache for CP stores, for PMA (mainstore) fetches/loads, and for cache-to-cache loads, and with uncorrectable error recovery cache fetch and store logic injects `Special UEs` into the cache when loads cannot be blocked and abends CP jobs for UEs during CP stores, for UEs from PMA, for UEs from remote cache, and for UEs from local cache.

Abstract: The present invention is a digital FM voice paging system which uses digital signal processing (including D/A conversion and data compression) to transmit voice pager data over existing FM broadcast subcarriers.

Abstract: A memory request protocol allows a memory request to be withdrawn or "cancelled" without penalty so no memory resource is wasted in doing so during an assigned "cancel window". When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or "cancel window".

Abstract: A memory control device, having a common synchronous interface coupled thereto, for accessing asynchronous memory devices, as well as other synchronous devices. The memory control device receives, via the synchronous interface, a command having a synchronous format, and translates at least a portion of the command from the synchronous format to an asynchronous format. The command in the asynchronous format is then used to access an asynchronous memory device. The asynchronous memory device can have one of various formats, each of which is supported by the memory control device. The memory control device emulates synchronous memory devices for the system memory controller coupled to the memory control device, even when asynchronous devices are accessed. The memory control device can also translate commands from one synchronous format to another synchronous format such that memory devices of the another synchronous format can be accessed.

Abstract: A method and device for tracking a bus transaction between first and second agents coupled to a bus includes issuing a request for the transaction by the first agent, storing information regarding the transaction in a buffer, and deleting the information regarding the transaction from the buffer if the first agent receives an indication that the second agent will not issue a retry.

Abstract: The present invention is a digital FM voice paging system which uses digital signal processing (including D/A conversion and data compression) to transmit voice pager data over existing FM broadcast subcarrriers.

Abstract: An apparatus and method is discussed using a parity check matrix in order to acheive correction and detection of errors particularly pertaining to detection data fetched from a wrong address. The code structure enhances utilization of chip reliability by encoding and decoding digital signals through the utilization of a parity check matrix and parity bits generated from system address bits of a computer system with k symbols and b bits per symbol.

Abstract: A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.

Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.

Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.

Abstract: A hand brake mechanism for a central processing unit cabinet comprising a base and a handle, wherein the base is fixed on the bottom of the cabinet and located between two wheels provided on the cabinet. A pair of engaging rods, each engaging rod having a guide pin at one end, are provided on both sides of the base. The handle is combined with the base, and is slidable thereon. There are a pair of guide plates provided on the handle at a location corresponding respectively to each of the engaging rods. The guide pin of the engaging rod comes into contact with the edge of the guide plate. When pushing or pulling the handle, the guide pin slides along the guide plate, and the engaging rod moves axially, to engage or disengage the wheels of the CPU cabinet.

Abstract: A meat emulsion containing a mix of meat materials with the emulsion having a protein to fat ratio of at least about 1.5:1 and a moisture content in the range of about 45% to 80% is processed under conditions which rapidly heat the emulsion to a temperature of above the boiling point of water at which temperature protein coagulation proceeds at a very rapid rate. The hot meat emulsion is introduced by centrifugal force into a confined holding tube in which the emulsion is retained for a relatively short period of time during which the protein coagulates to set the emulsion and provide a firm meat emulsion product, with the emulsion being maintained at a pressure greater than the vapor pressure of emulsion water.