Patents by Inventor William Wu

William Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160217468
    Abstract: A method and system for facilitating online payments are disclosed. According to one aspect of the present invention, a payment agreement is established at a payment service provider that defines terms of a payment relationship between a merchant and a user. The establishing of the payment agreement includes linking the payment agreement with a payment account of the merchant or user stored at the payment service provider. After establishing the payment agreement, a payment request associated with a transaction is received, whereby the payment request includes a unique identifier to identify the payment agreement stored at the payment service provider. Based on a verification that the payment request complies with terms of the payment agreement, the payment request is processed.
    Type: Application
    Filed: April 5, 2016
    Publication date: July 28, 2016
    Inventors: Hugo Olliphant, Franck Chastagnol, Yi-Ling Su, William Wu, Chris Brown, Thach Dang, Thomas Veino, Carol Gunby, Peter Zhe Chu, Steven Chen
  • Publication number: 20160147435
    Abstract: A system and method for receiving a user interaction with a user interface of a client device, determining a current communication mode and a desired communication mode, where the desired communication mode is determined based on the user interaction received by the sensor module. The system further sets the desired communication mode as the current communication mode, and causes presentation of a user interface of the client device based on the desired communication mode being set as the current communication mode.
    Type: Application
    Filed: November 23, 2015
    Publication date: May 26, 2016
    Inventors: Jonathan Brody, Matthew Hanover, Chamal Samaranayake, William Wu
  • Publication number: 20160125456
    Abstract: Various embodiments use contextual data to improve the targeting of advertising campaigns to consumers. Contextual data may include, e.g., data pertaining to products purchased or sold, places associated with a purchase or sale, and persons involved in the purchase or sale transaction. The collected contextual data may have a temporal component and a location component. The collected contextual data also has a location component, meaning that the data is associated with a particular coordinate, address, region, or other location. Time and location information may be used to recognize that sales patterns vary based on various factors. Associating a timestamp and a location with each piece of contextual data allows the system in some embodiments to subsequently improve advertising campaign targeting using the timing and location data as described herein in some embodiments.
    Type: Application
    Filed: November 3, 2014
    Publication date: May 5, 2016
    Inventors: Wan-Chung William Wu, Thomas Opdycke
  • Patent number: 9317841
    Abstract: A method and system for facilitating online payments are disclosed. According to one aspect of the present invention, a payment agreement is established at a payment service provider that defines terms of a payment relationship between a merchant and a user. The establishing of the payment agreement includes linking the payment agreement with a payment account of the merchant or user stored at the payment service provider. After establishing the payment agreement, a payment request associated with a transaction is received, whereby the payment request includes a unique identifier to identify the payment agreement stored at the payment service provider. Based on a verification that the payment request complies with terms of the payment agreement, the payment request is processed.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: April 19, 2016
    Assignee: PayPal, Inc.
    Inventors: Hugo Olliphant, Franck Chastagnol, Yi-Ling Su, William Wu, Chris Brown, Thach Dang, Thomas Veino, Carol Gunby, Peter Chu, Steve Chen
  • Publication number: 20160100892
    Abstract: A surgical drape for interventional cardiology, the surgical drape comprising: a substantially rectangular impervious layer, wherein the substantially rectangular impervious layer is configured to be draped over a patient; one or more absorbent layers attached on one side of the substantially rectangular impervious layer, wherein the one or more absorbent layers cover substantially the substantially rectangular impervious layer; one or more pedal access regions through the substantially rectangular impervious layer and the one or more absorbent layers; one or more femoral access regions through the substantially rectangular impervious layer and the one or more absorbent layers; and one or more radial access regions through the substantially rectangular impervious layer and the one or more absorbent layers. Other embodiments are described and claimed.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 14, 2016
    Inventor: William Wu
  • Publication number: 20160085863
    Abstract: A system and method for a media filter publication application are described. The media filter publication application receives a content item and a selected geolocation, generates a media filter based on the content item and the selected geolocation, and supplies the media filter to a client device located at the selected geolocation.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Inventors: Nicholas Richard Allen, Sheldon Chang, Timothy Michael Sehn, William Wu
  • Patent number: 9235530
    Abstract: A system and method for clearing data from a cache in a storage device is disclosed. The method may include analyzing the cache for the least recently fragmented logical group, and evicting the entries from the least recently fragmented logical group. Or, the method may also include analyzing compaction history and selecting entries for eviction based on the analysis of the compaction history. The method may also include scheduling of different eviction mechanisms during various operations of the storage device. The system may include a cache storage, a main storage and a controller configured to evict entries associated with a least recently fragmented logical group, configured to evict entries based on analysis of compaction history, or configured to schedule different eviction mechanisms during various operations of the storage device.
    Type: Grant
    Filed: May 31, 2010
    Date of Patent: January 12, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: William Wu, Steven Sprouse, Sergei Anatolievich Gorobets, Alan Bennett, Ameen Aslam
  • Publication number: 20150272183
    Abstract: The present invention relates to a method of producing an aromatised food or beverage product, wherein an aroma fraction is obtained from a plant extract, said aroma fraction is being contacted with an oil to remove undesired aroma compounds, and the aroma fraction from which undesired compounds have been removed are combined with a food or beverage composition to produce an aromatised food or beverage product.
    Type: Application
    Filed: November 29, 2013
    Publication date: October 1, 2015
    Inventors: Scott A. Westfall, William Wu, Annette Michelle Birch, Amber Christine Scarlatos
  • Patent number: 9104327
    Abstract: A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: August 11, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Sergey Anatolievich Gorobets, William Wu, Steven T. Sprouse
  • Publication number: 20150213182
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Application
    Filed: April 6, 2015
    Publication date: July 30, 2015
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Patent number: 9063862
    Abstract: A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: June 23, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: William Wu, Sergey Anatolievich Gorobets, Steven Sprouse, Alan Bennett
  • Patent number: 9003338
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Patent number: 8848445
    Abstract: A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: September 30, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Steven T. Sprouse, Sergey Anatolievich Gorobets, William Wu, Alan Bennett, Marielle Bundukin
  • Publication number: 20140282305
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Publication number: 20140281132
    Abstract: A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Marielle Bundukin, King Ying Ng, Steven T. Sprouse, William Wu, Sergey Anatolievich Gorobets, Liam Parker, Alan David Bennett
  • Publication number: 20140239427
    Abstract: Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Publication number: 20140126274
    Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Sean LEE, William Wu SHEN, Yun-Han LEE
  • Patent number: 8701073
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-min Fu, William Wu Shen, Po-Hsiang Huang, Meng-Fu You, Chi-Yeh Yu
  • Publication number: 20140096102
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.
    Type: Application
    Filed: November 21, 2012
    Publication date: April 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-min FU, William Wu SHEN, Po-Hsiang HUANG, Meng-Fu YOU, Chi-Yeh YU
  • Patent number: 8626986
    Abstract: A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: January 7, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: William Wu, Shai Traister, Jianmin Huang, Neil David Hutchison, Steven Sprouse