METHOD FOR IMPROVING WRITABILITY OF SRAM MEMORY

Abstract

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(e) to U.S. provisional patent application 61/382,243 filed on Sep. 13, 2010, which application is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosed technology relates to a method for writing a value in an SRAM (static random access memory) cell, and particularly to a technique for improving the writability of SRAM memory cells, such as 6T and 8T SRAM cells. The disclosed technology also relates to an SRAM memory adapted for using this method, and to an electronic device comprising such an SRAM memory.

2. Description of the Related Technology

The usage of SRAM is continuously increasing in system-on-chip (SOC) designs. Process technology scaling has contributed remarkably in improving the performance of and area density of system-on-chip, whereby the SRAM cell typically utilizes the minimum sized transistor in order to realize a high density. However, SRAM scaling has become extremely difficult in the advanced technology nodes (e.g. 65 or 32 nm Low Power CMOS technology).

SRAM bit cell functional parameter degradation due to increasing variability and decreasing power supply is of utmost concern. One of the problems is writability, causing write-failures in the SRAM cell. A failure to write occurs when the access transistor is not strong enough to overpower the pull-up PMOS and pull the internal node to ground.

Several write assist techniques to improve writability at low supply voltages are described in the art, the two most important techniques being Boosted Word-line (BWL) [1] and Negative Bit Line (NBL) [2]. The word line boosting scheme (BWL) relative to VDD of SRAM cells reduces the stability (SNM_READ) of the half selected SRAM cells on the same word line, which puts a higher limit on the value of word line boosting applied. The negative bit-line technique (NBL) requires the VSS side of the bit-line to be negative biased. This increases the risk of forward biasing PN Junctions (latch-up) and puts the limit on the value of an applied negative boost.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

Certain inventive aspects relate to a technique for improving the writability of an SRAM cell. Improving writability means decreasing the risk of write failures.

One inventive aspect relates to a method for writing a bit-value in at least one SRAM cell, part of an SRAM memory, the SRAM cell comprising a pair of cross-coupled invertors for storing the bit-value, the invertors being connected between a local ground node and a local supply node, each invertor being connected via its input to one of a pair of complementary bitlines via one of a pair of access transistors for writing the bit-value in the SRAM cell, the pair of access transistors being controllable by a write_wordline. The method may comprise a) applying a global supply voltage and a global ground voltage to the SRAM memory, b) pre-charging one of the bitlines of the pair of complementary bitlines to the global ground voltage, and pre-charging the other bitline of the pair of complementary bitlines to a complementary voltage, depending on the bit-value to be written in the SRAM cell, c) providing a first voltage to the local ground node, the first voltage having a value higher than the value of the global ground voltage by a first predefined amount, d) applying a second voltage to the write_wordline, the second voltage having a value higher than the value of the global supply voltage by a second predefined amount, and e) applying a third voltage to the local supply node, the third voltage having a value higher than the value of the global supply voltage by a third predefined amount.

With complementary voltage is meant a “high” voltage, complementary to the “low” voltage.

Applying the first voltage higher than the global ground voltage to the ground node reduces the strength of the aids in overpowering the state of the cell, which improves write-ability. Applying the second voltage higher than the value of the global supply voltage to the write-word line increases the strength of the access transistors, which further improves write-ability. Applying the third voltage to the local supply node solves the problem of “half select” cells located on the same row of the SRAM cell to be written (i.e. SRAM cells sharing the same write-wordline), and solves data retention issues with the SRAM cells present on the same column (i.e. sharing the same pair of bitlines), due to the raised ground voltage.

Although similar in many respects to the negative bitline technique of the prior art, an important advantage of the method in one inventive aspect is that it can avoid the risk of forward biasing PN junctions (latch-up), which puts a limit on the value of the applied negative “boost” (i.e. the difference between the negative voltage applied to the bitline and the ground voltage). This risk can be avoided because in the method according to one inventive aspect the voltage with the lowest value, i.e. the global ground voltage is preferably applied as the bulk voltage of the SRAM memory.

The first amount may be equal to or higher than the third amount and the second amount is equal to or higher than the third amount. This can further improve the writability of the cell.

The first and second and third amount may be substantially equal. This offers the advantage that writability is improved while readability is not degraded. In addition, using the same voltage for the write_wordline and for the local supply voltage (during a write cycle) has the advantage of requiring less different voltages.

The SRAM cells may be grouped in SRAM words, and the SRAM words may be arranged in rows of SRAM cells sharing the write_wordline, and in columns of SRAM cells sharing the pair of bitlines, and wherein the first voltage is applied only to the column, and the second and third voltage are applied only to the row containing the SRAM word which is to be written, and preferably only when actually being written.

By providing the increased voltages only to the column and row containing the SRAM word being written, and not to the entire SRAM memory, the integrity of the other SRAM cells is maximally secured, and energy can be saved. By applying the increased voltages to the entire column and row containing the SRAM word being written, and not to the single SRAM word to be written, huge selection overhead can be saved.

One inventive aspect relates to an SRAM memory. The memory comprises a) a plurality of SRAM cells, each SRAM cell comprising a pair of cross-coupled invertors for storing a bit-value, the invertors being connected between a local ground node and a local supply node, each invertor being connected via its input to one of a pair of complementary bitlines via one of a pair of access transistors for writing the bit-value in the SRAM cell, the pair of access transistors being controllable by a write_wordline, b) a source voltage applying module for applying a global ground voltage and a global supply voltage to the SRAM memory, c) a precharging module for precharging one of the bitlines of the pair of complementary bitlines of the SRAM cell to the global ground voltage, and for precharging the other bitline of the pair of complementary bitlines to a complementary voltage, depending on the bit-value to be written in the SRAM cell, d) a first voltage applying module for applying a first voltage to the local ground node, the first voltage having a value higher than the value of the global ground voltage by a first predefined amount, a second voltage applying module for applying a second voltage to the write_wordline for enabling its pair of access transistors, the second voltage having a value higher than the value of the global supply voltage by a second predefined amount, and e) a third voltage applying module for applying a third voltage to the local supply node, the third voltage having a value higher than the value of the global supply voltage by a third predefined amount.

Such an SRAM memory can be used for implementing the above method.

The first amount may be equal to or higher than the third amount and the second amount is equal to or higher than the third amount.

The first voltage applying module may comprise a first switching module for disconnecting the local ground node of the SRAM cell from the global ground voltage and for connecting the local ground node to a first voltage node to which the first voltage value is applied.

The second voltage applying module may comprise a second switching module for connecting the write_wordline of the SRAM cell to a second voltage node to which the second voltage value is applied.

The third voltage applying module may comprise a third switching module for disconnecting the local supply node of the SRAM cell from the global supply voltage and for connecting the local supply node to a third voltage node to which the third voltage value is applied.

The SRAM may further comprise control circuitry adapted for generating control signals for controlling the first and second and third switching module, such that during a write cycle to the SRAM cell, the local ground node is connected to the first voltage node, the write_wordline is connected to the second voltage node, and the local supply node is connected to the third voltage node.

The increased voltages may be applied by such first, second and third switching module connected to the local ground nodes, write_wordlines and the local supply nodes of the SRAM memory.

The SRAM cells may be grouped in SRAM words, and the SRAM words may be arranged in rows of SRAM cells sharing the write_wordline and in columns of SRAM cells sharing the pair of complementary bitlines and sharing the local ground node, and wherein the first switching module is adapted for applying the first voltage to the column, and the second switching module is adapted for applying the second voltage to the row of the SRAM word to be written, and the third switching module is adapted for applying the third voltage to the row and/or column of the SRAM word to be written.

By providing a structure having local ground nodes that can be switched at column level, and having local supply nodes that can be switched at row level, as opposed to switching each SRAM cell individually, large area savings can be achieved, without wasting too much energy. By switching the local ground and local supply voltages instead of switching the global ground and global supply voltages, and by switching them only during a write cycle, huge energy savings can be achieved.

In one aspect the second voltage node is the same as the third voltage node. This offers placement (area, layout, routing) advantages in that the SRAM cell only needs one “high voltage node”, and (as will be shown further) the stability of unselected cells is improved, and in that less different voltages need to be supplied.

One inventive aspect relates to an electronic device comprising such an SRAM memory.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure is further elucidated in the appending figures and figure description explaining preferred embodiments of the disclosure. Note that the figures are not necessarily drawn to the scale. The figures are intended to describe the principles of the disclosure.

FIG. 1 shows a circuit diagram of a 6T SRAM cell.

FIG. 2 shows the structure of FIG. 1 in more detail.

FIG. 3 shows a circuit diagram of an 8T SRAM cell.

FIG. 4 shows a write cycle performed on the 6T SRAM cell of FIG. 2, and illustrates how Vt mismatch may cause write failures.

FIG. 5 shows the principle of the negative bitline technique known in the art.

FIG. 6 shows one embodiment of the mimicked negative bitline MNBL technique.

FIG. 7 shows a high-level block diagram of an embodiment of the SRAM memory according to one embodiment.

FIG. 8 shows the SRAM array of FIG. 7 in idle state (no write action).

FIG. 9 shows the SRAM array of FIG. 7 during a write operation to the selected SRAM word.

FIG. 10 shows the voltages applied to the different zones of the SRAM memory of FIG. 9.

FIGS. 11A and 11B show the effect of increasing the local ground voltage, FIG. 11A for an SRAM cell to be written, FIG. 11B for an inactivated SRAM cell in the same column as the selected SRAM cell.

FIGS. 12A and 12B show the effect of increasing the local ground voltage and the write_wordline voltage, in FIG. 12A for an SRAM cell to be written, in FIG. 12B for an inactivated SRAM cell in the same row.

FIGS. 13A and 13B show the effect of subsequently increasing the local supply voltage, in FIG. 13A for an SRAM cell to be written, in FIG. 13B for an inactivated SRAM cell in the same row.

FIG. 14 shows plots of the write margin for different values of Δv1, Δv2 and Δv3, for supply voltage VDD=0.55V in 65 nm LP technology.

FIG. 15 shows plots of the static noise margin SNM Read for different values of Δv1, Δv2, Δv3, for supply voltage VDD=0.55V in 65 nm LP technology.

FIG. 16 shows a comparison of the performance of the mimicked negative bitline technique (MNBL) versus the Negative Bitline technique (NBL).

FIGS. 17A, 17B, 17C show an example of the first, second and third switching module.

FIG. 18 shows the improvement of the write margin obtained by the preferred embodiment of the MNBL technique for a predefined amount of 0.10 V.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.

Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. The terms are interchangeable under appropriate circumstances and the embodiments of the disclosure can operate in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments of the disclosure described herein can operate in other orientations than described or illustrated herein.

The term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting of only components A and B. It means that with respect to the present disclosure, the only relevant components of the device are A and B.

Certain embodiments relate to static random access memory (SRAM), and in particular, to a technique for improving the writability of SRAM cells for advanced technology nodes (65 nm LP CMOS and beyond).

In the past, process technology scaling has contributed remarkably in improving the performance of and area density of system-on-chip (SoC) in general, and SRAM in particular. But the SRAM scaling has become extremely difficult in the advanced technology nodes (65 nm LP CMOS and beyond). This is mainly because of the fact that, in order to realize the high density, the SRAM cell utilizes the minimum sized transistor which is highly susceptible to Vt (threshold voltage) mismatches. The Vt mismatch is mainly caused by a do-pant-ion implantation variation and gate edge roughness and is inversely proportional to the transistor size. SRAM bit cell functional parameter degradation due to increasing variability and decreasing power supply is of utmost concern. The process variations are classified into two categories one which result in the differences in the characteristics of the neighboring devices on the same die (intra die) and the other which effects all the devices on a die in the same manner (inter die). The intra die variations are in inverse proportion to the square root of the transistor channel area. With the technology scaling the shrinking transistor dimensions result in large intra die variations which degrade the read current I_READ, the read static noise margin SNM_READ and the write margin of the SRAM cell. The classic design approach in order to meet the challenges posed by the technology scaling relies on the upsizing and on the extra design margins. This upsizing and too much insertion of the design margins result in a degradation of energy consumption and performance. Therefore, circuit design techniques which improve the operating margins of SRAM without increasing the energy consumption are required. One embodiment focuses on improving the write margin of an SRAM cell.

In order to better understand certain embodiments, first a 6T SRAM will be described, as shown in FIGS. 1 and 2.

FIG. 1 shows a block diagram of a traditional 6T SRAM cell. FIG. 2 shows the structure of FIG. 1 in more detail. Each SRAM cell includes a pair of inverters INV1, INV2 that are cross-coupled (i.e. the input of one invertor is connected to the output of the other invertor) for operating together in a loop to store true and complement data Q, Q\ on the nodes N1, N2. The local true bitline BL and the local complement bitline BL\ are connected to the SRAM cell by a pair of access transistors Mpl, Mpr to respective true and complement sides of the invertors. The bitlines BL, BL\ are typically grouped in bit slices (not shown) of a multiple of SRAM cells. A wordline WL provides the gate input to the access transistors Mpl, Mpr. A particular wordline WL is activated (also called “enabled”) for turning on the access transistors of the selected SRAM cell to perform a read or write operation. Associated with each bit slice are pre-charge true and complement circuits coupled to the respective local true and complement bitlines BL and BL\, write true and write complement circuits, and a local evaluate circuit (not shown). Since true and complement data is stored in the SRAM memory cell, either the pre-charged high true local bitline BL will be discharged if a “zero” was stored on the true side, or the pre-charged high complement bitline BL\ will be discharged if a “zero” was stored on the complement side. The local bitline BL or BL\ connected to the “one” side will remain in its high pre-charged state during a write access.

FIG. 2 shows the six individual transistors (hence 6T) of the standard 6T SRAM cell of FIG. 1: a left and right access transistor Mpl, Mpr, a left pull-up PMOS transistor Mul and a left pull-down NMOS transistor Mdl forming the first invertor INV1, a right pull-up PMOS transistor Mur and a right pull-down NMOS transistor Mdr forming the second invertor INV2. The input N1 of the first inventor INV1 is coupled with the output of the second invertor INV2, and vice versa. In this way they form a loop which stores the data. In fact they store two complementary values, in this example a high voltage value H on the right side, and a low voltage value L on the left side.

FIG. 3 shows a block diagram of a traditional 8T SRAM cell. Comparison of the 8T SRAM cell with the 6T SRAM cell of FIG. 2 shows that a read port is added comprising two additional transistors T7, T8, a read bitline RBL is added and a read_wordline RWL is added. Note that the read_— and write_wordline RWL, WWL, and the read_— and write_bitlines RBL, WBL, WBL\ are completely separate. As known in the art, this provides a solution to readability problems of the SRAM cell, at the expense of increased area, but does this not solve the writability problem of the 6T SRAM cell, which is an aim of one embodiment.

FIG. 4 shows a write operation of the standard 6T SRAM cell initially storing a high value H at the right node N1 and a low value L in the left node N2. To change the value in the SRAM cell, i.e. to write a high value H at the left node N2, (and a low value in the right node N1), the voltage at the right node N1, i.e. the input of the first invertor INV1 needs to be pulled below the trip point of the first inverter INV1 that drives the left node N2. This should occur when the write_wordline WWL is asserted by applying voltage Vwl equal to VDD to the access transistors Mpl, Mpr, the word_bitline WBL being pre-charged to the supply voltage VDD, the complementary word_bitline WBL\ being pre-charged to ground VSS. If everything works fine, a discharge current IMur will then flow through the right pull-up transistor Mur and through the right access transistor Mpr to the complementary write_bitline WBL\, causing the voltage of node N1 to drop below the trip point of the first invertor INV1, causing the voltage at the left node N2 to go high, which in turn causes the value of the second invertor INV2 to go low.

However, an increased strength of the right pull-up transistor Mur or a decreased strength of the right access transistor Mpr due to process variations can impede the discharge process through the right access transistor Mpr. Furthermore, process variations may also reduce the trip point of the first inverter INV1 resulting in a write failure. For a successful write operation, the current IMpr through the right access transistor Mpr should be higher than the current IMur through the right pull-up transistor Mur. The write margin, abbreviated WM, is determined by the current ratio of the pull-up PMOS transistors Mul, Mur in relation to the pass access NMOS transistors Mpl, Mpr. A successful write operation can be achieved by increasing the strength of the write access NMOS pass transistors Mpl, Mpr or by decreasing the strength of the pull-up PMOS transistors Mul, Mur, or both.

The techniques that have been proposed in the art for improving the write margin WM can broadly be classified into two categories, a first category of techniques which target increasing the strength of write NMOS access like WL-boosting [1] and Negative Bitline boosting [2], and a second category of technique which target decreasing the strength of the latch structure like lowering the supply voltage VDD [3] and raising the ground voltage VSS [4]. Increasing the strength of the write NMOS access transistors Mpr, Mpl is more effective for improving the write margin WM of an SRAM cell than reducing the strength of the latch structure.

Increasing the voltage level of the write_wordline WWL relative to VDD power supply of the SRAM cell, a technique known as “wordline boost” increases the strength of the NMOS write access transistors Mpr, Mpl for avoiding the write failure. However, the “word line boosting” technique reduces the stability (SNM_READ) of the half selected SRAM cells on the same word line WL. Half selected SRAM cells are cells not being written to, but sharing an asserted wordline WL with other SRAM cells being written to. The reduced static noise margin SNM_READ for the half selected SRAM cells on the same word line WL puts a higher limit on the value of word line boosting applied.

FIG. 5 illustrates a technique known as “negative bitline”, abbreviated “NBL”, where the strength of the write access transistor Mpr is increased by lowering the voltage of the write_bitline WBL\ to a negative voltage (i.e. a voltage below the ground VSS). This increases the gate-to-source voltage V_GS and the drain-to-source voltage V_DS of the pass transistor Mpr. This accelerates the discharge process and the write failure is avoided. The negative bitline bias does not directly impact the half select bits. Although the write_bitlines WBL, WBL\ are typically shared between several SRAM cells, there is no problem for the unselected SRAM cells because the write_wordlines WWL for those unselected cells are at the ground voltage VSS, and thus not activated. The increase in the gate-to-source voltage V_GS of the access NMOS transistors for the unselected cells is kept lower than their threshold voltage Vt. In other words, the SNM_READ with the “negative bitline concept” is not degraded. However, the negative bitline technique requires one of the bitlines WBL, WBL\ to be negatively pre-charged. This increases the risk of forward biasing PN junctions (latch-up) and puts the limit on the value of an applied negative boost. In addition, a negative supply voltage is required.

FIG. 6 shows a solution proposed by one embodiment for solving the writability problem, referred to as “mimicked negative bitline”, abbreviated MNBL. In the write operation for the standard 6T or 8T SRAM cell (FIGS. 1-3) the write_wordline voltage Vwl during a write operation is the supply voltage VDD, and the precharge voltages of the true and complement word_bitlines WBL, WBL\ are VDD and VSS (or vice versa, depending on the data to be written). In the embodiment of FIG. 6, the write_bitlines WBL, WBL\ are also pre-charged to the supply and ground voltages VDD and VSS (or vice versa), but the supply and ground voltages of the selected SRAM cell, and the control voltage Vwl of the write_wordline WWL are increased to a value higher than the normal supply and ground voltages VDD, VSS. This enhances the gate-to-source V_GS and drain-to-source V_DS voltages of the NMOS access transistor Mpr, thereby increasing the discharge current IMpr. The strength of the pull-up transistors Mul, Mur does not change because the effective cell supply ((VDD+ΔV)-(VSS+ΔV)) remains unchanged. Although quite similar in many respects to the negative bitline NBL technique (hence the name “mimicked negative bitline”), an important advantage of the MNBL technique is that it avoids the risk of forward biasing PN junctions (latch-up), because the voltage with the lowest value, i.e. the global ground voltage VSS is preferably applied as the bulk voltage of the SRAM memory, whereas in the standard NBL-technique, one of the bitlines was pre-charged to a value lower than VSS. If the “divided word line” architecture is used then there is no degradation of SNM read of unselected cells in the same row, but the data retention for the unselected cells in the same column for which the voltage of the local ground node LGN is raised to the first voltage VSS_high, may still be an issue. This can be remedied by also raising the local supply voltage LSN for the unselected cells in the same column, by applying the third voltage VDD_high also to the unselected cells of the column.

FIG. 7 shows a high-level block diagram of an embodiment of the SRAM memory according to one embodiment. It has a memory matrix (also known as memory array) comprising a plurality of SRAM words, each SRAM word comprising a plurality of SRAM cells. The SRAM memory of FIG. 7 is organized in columns and rows, and has a module for applying a global ground voltage VSS and a global supply voltage VDD to the SRAM memory, and for applying the global ground voltage VSS as bulk voltage to the SRAM memory, and data lines (not shown) for receiving data to be written, and address lines (not shown) for receiving an address for indicating the location where the data is to be written, and address decoding circuitry for selecting the SRAM word corresponding to the address, and pre-charging module for precharging one of the bitlines of the pair of complementary bitlines WBL, WBL\ of the SRAM cells of the selected SRAM word to the global ground voltage VSS, and for pre-charging the other bitline of the pair of complementary bitlines to a complementary voltage (e.g. VDD), or vice versa, depending on the data to be written in the SRAM cells of the selected SRAM word. Each row has a separate write_wordline WWL.

The SRAM word has a local ground node LGN and a local supply node LSN that can be decoupled from the global ground node VSS and the global supply node VDD. Depending on the implementation, the local ground node LGN may be connected to more than one SRAM word, e.g. to an entire column. Depending on the implementation, the local supply node LSN may be connected to more than one SRAM word, e.g. to an entire row.

The SRAM memory also has a first module, e.g. ground switching circuitry containing first switching module SW1 for applying either the global ground voltage VSS or a first voltage VSS_high to the invertors of the selected SRAM word, the first voltage having a value higher than the global ground voltage VSS by a first predefined amount ΔV1 larger than zero.

The SRAM memory also has a second module, e.g. worldline driver circuitry containing second switching module SW2 for applying either the global ground voltage VSS or a second voltage to the write_wordline WWL of the selected SRAM word, the second voltage having a value higher than the global supply voltage VDD by a second predefined amount Δv2 larger than zero.

The SRAM memory also has a third module, e.g. supply switching circuitry containing third switching module SW3 for applying either the global supply voltage VDD or a third voltage VDD_high to the invertors of the selected SRAM word, the third voltage having a value higher than the global supply voltage VDD by a third predefined amount ΔV3 larger than zero.

The SRAM memory also has control circuitry adapted for generating control signals for controlling the first and second and third switching module SW1, SW2, SW3, such that during a write cycle to the SRAM word, the local ground node LGN is connected to the first voltage node, the write_wordline WWL is connected to the second voltage node, and the local supply node LSN is connected to the third voltage node.

In an embodiment the complementary voltage VC is the global supply voltage VDD. In an embodiment the complementary voltage VC is the third voltage VDD_high. The global supply voltage VDD as well as the third voltage may be used for pre-charging the complementary bitlines WBL, WBL\. Depending on the implementation, either can be used. Using the third voltage VDD_high helps in increasing the rise time for the internal node Q\ if so desired.

FIG. 8 shows the SRAM array of FIG. 7 during idle mode. The voltages applied to the local ground nodes VSS1, VSS2, . . . , VSSm are all equal to the global ground voltage VSS. The voltages applied to the local supply nodes VDD_row1, VDD_row2, . . . VDD_rown are all equal to the global supply voltage VDD. The voltage of each write_wordline Vw11, Vw12, . . . , Vw1n are all equal to the global ground voltage VSS.

During a read action to the SRAM word located in the second row and the second column, the local ground voltage would remain VSS, and the local supply voltage would remain VDD, but the write_wordline Vw12 would go high to the global supply voltage VDD. In fact, that is the situation with 6T SRAM cells. For an SRAM memory having 8T SRAM cells, the write_wordline Vw12 would remain VSS, while the read_wordline RWL would go to VDD.

FIG. 9 shows the SRAM array of FIG. 7 during a write operation to the selected SRAM word, in this example located in the first column and the first row. First (not shown) the true and complement bitlines of the SRAM cells of the selected SRAM word are precharged to appropriate values, corresponding to the data to be written in the SRAM cells. Then the local ground voltage of the selected SRAM word is increased from VSS to VSS_high=VSS+Δv1, and the local supply voltage of the selected SRAM word is increased from VDD to VDD_high=VDD+Δv3, and the write_wordline WWL of the selected SRAM word is asserted by applying a voltage Vw1=VDD+Δv2 thereto.

In fact, in this example the local ground voltage of the entire column wherein the selected SRAM word is located is increased to VSS_high, and the local supply voltage of the entire row wherein the selected SRAM word is located is increased to VDD_high. This is not absolutely required however, but depends on the topology chosen. At one extreme, only the local ground and supply of the selected SRAM word may be increased, not the entire column or row, which would require minimal energy, but more silicon area. At the other extreme, the ground and supply of all the SRAM words of the entire SRAM memory may be increased, which would require minimum silicon area but large energy consumption. Changing the supply and ground voltages between the increased values VDD+ΔV, VSS+ΔV and the normal values VDD, VSS for every write cycle would involve frequent switching of huge capacitances (PMOS transistor gate-to-drain, NWELL diode capacitance of SRAM array, NMOS transistor gate-to-drain capacitance), which would increase the energy consumption and the delay for write cycles. The person skilled in the art can make an appropriate trade-off between these two extremes. The energy consumption overhead can be further reduced in software by clustering write cycles into consecutive instructions.

Although in FIG. 9 some unselected SRAM words experience an increased ground voltage and/or an increased supply voltage and/or an asserted write_wordline, no write operation will occur in these unselected SRAM words, as will be explained next.

FIG. 10 shows an example of the voltages applied in the different zones of the SRAM memory of FIG. 9, where a first zone Z1 contains the SRAM cells of the selected SRAM word in the activated column and the activated row, a second zone Z2 contains SRAM cells in the same row as the selected SRAM word but in a different column, a third zone Z3 contains SRAM cells in the same column as the selected SRAM word but in a different row, and a fourth zone Z4 contains SRAM cells in a different row and different column. The situation of the SRAM cells in the fourth zone Z4 is the same as that of FIG. 8, the situation of the SRAM cells in the third zone Z3 will be described in FIG. 11B, the situation of the SRAM cells in the first zone Z1 will be described in FIG. 13A, the situation of the SRAM cells in the second zone Z2 will be described in FIG. 13B.

The maximum allowable value of ΔV1 is preferably limited to avoid data retention issues (i.e. stability) of inactivated cells in the activated column (Zone Z3). The maximum allowable value of ΔV2 is preferably limited by data flip issues of inactivated cells in the activated row (zone Z4). The maximum allowable value of ΔV3 is preferably limited by write-ability for the activated word. The minimum allowable value of ΔV3 is preferably limited for data flip prevention in unselected cells in the activated row.

Optionally the local supply voltage LSN of the activate column may also be raised to the third voltage VDD_high, for maintaining the level of data retention of the unselected cells in the same column.

A preferred sequence of applying the voltages is illustrated in the FIGS. 11A-13B, but other sequences may also be used.

FIGS. 11A and 11B show the effect of increasing the local ground voltage from VSS to VSS_high=VSS+Δv1, in FIG. 11A for an SRAM cells of the selected SRAM word to be written, in FIG. 11B for an inactivated SRAM cell in the same column as the selected SRAM word. In a first step the local ground voltage of the activated column of the memory matrix is raised by a first predefined amount Δv1. It is desirable to first increase the voltage of the local ground node because of the latency associated in changing the voltage of highly the capacitive local ground lines for the activated column. Increasing the local ground voltage from VSS to VSS+Δv1 weakens the strength of the pull-down transistor Mtr and aids in improving writability of the SRAM cell. The reduction in the strength of the pull-down transistor Mtr is proportional to the first amount Δv1. This amount is preferably limited by data retention issues of inactivated cells on the activated column (zone Z3). FIG. 11A illustrates a first intermediate step for SRAM cells in zone Z1, FIG. 11B illustrates the final situation of SRAM cells in zone Z3.

FIGS. 12A and 12B show the effect of subsequently increasing the write_wordline voltage Vw1, in FIG. 12A for an SRAM cell to be written (zone Z1), in FIG. 12B for an inactivated SRAM cell in the same row (zone Z2). In a second step the voltage of the wordline WL is increased by a second predefined amount Δv2, which increases the strength of the access transistor Mpr and thus aids in improving writability. Applying Δv1+Δv2 together results in the higher values of write margin. The higher the value of Δv2, the higher the write margin will be. But the value of WL modulation Δv2 is preferably limited by the half-select condition of the inactivated cells in an activated column. FIG. 12A illustrates a second intermediate step for SRAM cells in zone Z1, FIG. 12B illustrates a first intermediate step of SRAM cells in zone Z2.

FIGS. 13A and 13B show the effect of subsequently increasing the local supply voltage from VDD to VDD_high =VDD+Δv3, in FIG. 13A for an SRAM cell to be written (zone Z1), in FIG. 13B for an inactivated SRAM cell in the same row (zone Z2). In a third step the local supply voltage of the activated row is raised by a third predefined amount Δv3. Increasing the local supply voltage reduces the probability of data flips arising due to the half select condition of the inactivated cells in the activated row. However, application of Δv3 reduces the write-ability of the asserted cells by increasing the strength of the pull-up transistor Mtr. The application of Δv1 reduces the strength of the pull-up transistor Mtr (increases writability) and application of Δv3 reduces the strength of the pull-up transistor Mtr (decreases writability, but increases cell stability). FIG. 13A illustrates the final situation for SRAM cells in zone Z1, FIG. 13B illustrates the final situation of SRAM cells in zone Z2.

The order of step 2 and step 3 can be interchanged, depending on the scenario (if cell stability is more important or writability is more important). It is also possible to share the local supply lines of SRAM cells and the wordline drivers, in which case step 2 and step 3 occur simultaneously and the value of the second amount Δv2 is equal to the value of the third amount Δv3.

Thus, applying the first voltage higher than the global ground voltage to the ground node reduces the strength of the PMOS pull up transistor. Weakening the PMOS transistors aids in overpowering the state of the cell, which improves write-ability. Applying the second voltage higher than the value of the global supply voltage to the write-word line increases the strength of the NMOS access transistors. Strengthening the NMOS transistors aids in overpowering the state of the cell, which further improves write-ability. Applying the third voltage to the local supply node solves the problem of “half select” cells located on the same row of the SRAM cell to be written, due to the applied write_wordline voltage, and solves the data retention issue with the SRAM cells present on the same column due to the raised ground voltage.

Prior art techniques either strengthen the NMOS transistor (e.g. WL boosting, Negative BL technique) or weaken the PMOS transistor (e.g., VDD-lowering or VSS-raising), but not both. In addition the value of boost applied in the prior art techniques is limited by the reduced stability of the SRAM cells on the selected row (in case of WL-boosting) or risk of latch-up (in case of negative bit-line) or data retention issue with SRAM cells present on the same column (in case of VDD lowering or VSS raising). These problems are avoided or at least reduced by applying the third voltage to the local supply node which solves the problem of “half select” cells due to the applied write_wordline voltage for SRAM cells located on the same row, and the data retention issue due to the raised ground voltage for SRAM cells located on the same column.

By applying the second voltage to the write_wordline, the gate-to-source voltage Vgs of the access transistor on the side for which the bit-line of the SRAM cell is precharged at global ground voltage for writing a “0”, is increased by the second predefined amount. Due to the application of the third voltage to the local supply node, the internal node storing “H” follows the source voltage of the PMOS transistor and also becomes higher by the third predefined amount, so that the drain-to-source voltage Vds of the access transistor on the side for which the bit-line of the SRAM cell is at a global ground voltage also increases. This results in a higher drive (i.e. a lower ON-resistance) as compared to the standard 6T SRAM technology, and improves the writability of the SRAM cell.

FIG. 14 shows plots of the write margin (shown as a cumulative distribution function) for different values of Δv1, Δv2 and Δv3, for supply voltage VDD=0.55V in 65 nm LP technology. As can be seen, the write margin improves by increasing the first and second amounts Δv1, Δv2 with respect to the third amount Δv3.

FIG. 15 shows plots of the static noise margin SNM Read as an indication of cell stability, for different values of Δv1, Δv2, Δv3 for inactivated cells in activated row (zone Z2), for supply voltage VDD=0.55V in 65 nm LP technology. As can be seen from the plots, the read margin and cell stability increase when the first and second amounts are higher than the third amount.

In the particular case when the second predefined amount Δv2 equals the third predefined amount Δv3, the increase in Vds and Vgs of the access transistor is the same as in the NBL technique (in which the bit-line voltage is a predefined amount below the global ground voltage). This is how the negative bitline mechanism is mimicked, however without going below the global ground voltage VSS, thereby avoiding the risk of latch-up.

In the particular case when the first predefined amount Δv1 equals the third predefined amount Δv3, the issue of stability, i.e. data retention for the un-accessed SRAM cells present on the same column, is solved because the net difference in the local supply voltage and local ground voltage remains unchanged.

By comparing FIGS. 14 and 15, it is clear that an optimum value for Δv1, Δv2, Δv3 is obtained by choosing Δv1=Δv2=Δv3. In this case the MNBL technique resembles a WRITE operation using the negative bit-line (NBL) technique best.

FIG. 16 shows a comparison of the (simulated) performance (in terms of write margin) of the mimicked negative bitline technique (MNBL) versus the known Negative Bitline technique (NBL). As can be seen from the graphs, the performance of the MNBL technique is quite comparable to that of the NBL technique. Surprisingly, it is even better than the NBL technique for small values of ΔV (up to approximately 0.20 V for the 65 nm technology node). The minor loss in performance for the higher values of ΔV (e.g. 0.20 V to 0.40 V) is due to the fact that the first voltage VSS_high with respect to the bulk-voltage VSS_Bulk applied to the SRAM memory or to the chip causes reverse body bias, resulting in an increased threshold voltage Vt of the NMOS transistors Mdl, Mdr, but the influence of reverse body bias on the threshold voltage Vt decreases with technology scaling. Besides, higher values of the difference voltage ΔV cannot be used with the NBL technique either, because of the risk of forward biasing PN junctions by applying voltages below the bulk level to the bitlines. There is no such risk involved with the MNBL technique because the bitlines are not precharged to a value below the global ground voltage VSS.

FIGS. 17A, 17B, 17C show an example of the first, second and third switching module SW1, SW2, SW3 respectively. The switches are controlled by control signals VSS tune, Vwl tune, VDD tune, generated in a control circuit (not shown). Such switches may e.g. be present in the VSS switching circuit block, and VDD switching circuit block, and WL driver block of FIG. 7.

FIG. 18 shows the improvement of the write margin obtained by the MNBL technique according to one embodiment, for a predefined amount of 0.10 V. As can be seen, this results in a factor thousand reduction of write failures for a global supply voltage VDD of 0.65 V.

One embodiment also relates to an electronic device, e.g. a system-on-chip (SoC) device for a portable application, e.g. wireless sensor nodes, or in stand-alone SRAM memory devices.

In an embodiment such electronic device comprises at least one local voltage generator for generating one of the voltages selected from the group of: the first voltage VSS_high, the global supply voltage VDD and the third voltage VDD_high. In this way less external voltages need to be supplied to the electronic device.

In an embodiment such electronic device comprises at least two local voltage generators for generating two of the voltages selected from the group of: the first voltage VSS_high, the global supply voltage VDD and the third voltage VDD_high. Such a device (chip) needs only one external supply, e.g. a battery, requires less pins, less external components on the PCB, and may occupy less board space. In an example, an external third voltage VDD_high of 0.75 V w.r.t. a global ground VSS is provided to the electronic device, and the first voltage VSS_high of 0.10 V and the global supply voltage of 0.65 V are generated internally using known DC-DC-convertor-techniques. Note that “generated internally” does not mean that all components (such as inductors or capacitors) need to be inside the chip, but it means that these voltages need not be applied from the outside. In another example, an external global voltage VDD of 0.65 V w.r.t. a global ground VSS is provided to the electronic device, and the first voltage VSS_high of 0.10 V and the third voltage of 0.75 V are generated internally.

The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the invention with which that terminology is associated.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the spirit of the invention. The scope of the invention is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Each of the following references is incorporated herein by references in its entirety.

REFERENCES

[1] S. Cosemans, W. Dehaene, F. Catthoor, “A 3.6 pJ/Access 480 MHz, 128 kbit On-Chip SRAM with 850 MHz Boost Mode in 90 nm CMOS with Tunable Sense Amplifiers,” IEEE J.Solid State Circuits, pp 2065-2077, July 2009.

[2] Shibata et al., “A 0.5V 25 MHz 1-mW 256 Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment—Sure Write Operation by Using Step-Down Negatively Overhead Bitline Scheme”, IEEE J.Solid-State Circuits pp. 728-742, March 2006.

[3] M. Yamaoka et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing”, ISSCC Dig. Tech. Papers, pp 480-481, Feb 2005

[4] Yamaoka M et al., “ A 300 MHz 25 uA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor” in IEEE ISSCC, Feb 2004, pp. 494-495.

Claims

1. A method of writing a bit-value in at least one static random access memory (SRAM) cell, the SRAM cell being a part of an SRAM memory, the SRAM cell comprising a pair of cross-coupled invertors for storing the bit-value, the invertors being connected between a local ground node and a local supply node, each invertor being connected via its input to one of a pair of complementary bitlines via one of a pair of access transistors for writing the bit-value in the SRAM cell, the pair of access transistors being controllable by a write_wordline, the method comprising:

a) applying a global supply voltage and a global ground voltage to the SRAM memory;

b) pre-charging one of the bitlines of the pair of complementary bitlines to the global ground voltage, and pre-charging the other bitline of the pair of complementary bitlines to a complementary voltage, depending on the bit-value to be written in the SRAM cell;

c) providing a first voltage to the local ground node, the first voltage having a value higher than the value of the global ground voltage by a first predefined amount;

d) applying a second voltage to the write_wordline, the second voltage having a value higher than the value of the global supply voltage by a second predefined amount; and

e) applying a third voltage to the local supply node, the third voltage having a value higher than the value of the global supply voltage by a third predefined amount.

2. The method according to claim 1, wherein the first amount is equal to or higher than the third amount and the second amount is equal to or higher than the third amount.

3. The method according to claim 1, wherein the process c) comprises decoupling the local ground node from the global ground voltage, and coupling the local ground node to a first voltage node to which the first voltage is applied.

4. The method according to claim 1, wherein the process e) comprises decoupling the local supply node from the global supply voltage, and coupling the local supply node to a third voltage node to which the third voltage is applied.

5. The method according to claim 1, wherein the complementary voltage in the process b) is the global supply voltage.

6. The method according to claim 1, wherein the complementary voltage in the process b) is the third voltage.

7. The method according to claim 1, wherein the first and the second and the third amount are substantially equal.

8. The method according to claim 1, wherein each of the first and second and third amount is a voltage in the range of 0.05V to 0.40V.

9. The method according to claim 1, wherein each of the first and second and third amount is a voltage in the range of 0.10V-0.30V.

10. The method according to claim 1, wherein the SRAM cells are grouped in SRAM words, and the SRAM words are arranged in rows of SRAM cells sharing the write_wordline, and in columns of SRAM cells sharing the pair of bitlines, and wherein the first voltage is applied only to the column, and the second and third voltage are applied only to the row containing the SRAM word which is to be written.

11. An SRAM memory comprising:

a plurality of SRAM cells, each SRAM cell comprising a pair of cross-coupled invertors for storing a bit-value, the invertors being connected between a local ground node and a local supply node, each invertor being connected via its input to one of a pair of complementary bitlines via one of a pair of access transistors for writing the bit-value in the SRAM cell, the pair of access transistors being controllable by a write_wordline;

a source voltage applying module configured to apply a global ground voltage and a global supply voltage to the SRAM memory;

a precharging module configured to precharge one of the bitlines of the pair of complementary bitlines of the SRAM cell to the global ground voltage and to precharge the other bitline of the pair of complementary bitlines to a complementary voltage, depending on the bit-value to be written in the SRAM cell;

a first voltage applying module configured to apply a first voltage to the local ground node, the first voltage having a value higher than the value of the global ground voltage by a first predefined amount;

a second voltage applying module configured to apply a second voltage to the write_wordline for enabling its pair of access transistors, the second voltage having a value higher than the value of the global supply voltage by a second predefined amount;

a third voltage applying module configured to apply a third voltage to the local supply node, the third voltage having a value higher than the value of the global supply voltage by a third predefined amount.

12. The SRAM memory according to claim 11, wherein the first amount is equal to or higher than the third amount and the second amount is equal to or higher than the third amount.

13. The SRAM memory according to claim 11, wherein:

the first voltage applying module comprises a first switching module configured to disconnect the local ground node of the SRAM cell from the global ground voltage and to connect the local ground node to a first voltage node to which the first voltage value is applied;

the second voltage applying module comprise a second switching module configured to connect the write_wordline of the SRAM cell to a second voltage node to which the second voltage value is applied; and

the third voltage applying module comprises a third switching module configured to disconnect the local supply node of the SRAM cell from the global supply voltage and for connecting the local supply node to a third voltage node to which the third voltage value is applied.

14. The SRAM memory according to claim 13, further comprising control circuitry configured to generate control signals for controlling the first and second and third switching module, such that during a write cycle to the SRAM cell, the local ground node is connected to the first voltage node, the write_wordline is connected to the second voltage node, and the local supply node is connected to the third voltage node.

15. The SRAM memory according to claim 11, wherein the second voltage node is the same as the third voltage node.

16. The SRAM memory according to claim 11, wherein each SRAM cell comprises a 6T SRAM cell.

17. The SRAM memory according to claim 11, wherein each SRAM cell comprises an 8T SRAM cell.

18. The SRAM memory according claim 13, wherein the SRAM cells are grouped in SRAM words, and the SRAM words are arranged in rows of SRAM cells sharing the write_wordline and in columns of SRAM cells sharing the pair of complementary bitlines and sharing the local ground node, and wherein the first switching module is configured to apply the first voltage to the column, and the second switching module is configured to apply the second voltage to the row of the SRAM word to be written, and the third switching module is configured to apply the third voltage to the row and/or column of the SRAM word to be written.

19. An electronic device comprising the SRAM memory according to claim 11, the device further comprising at least one local voltage generator configured to generate one of the voltages selected from the group of: the first voltage, the global supply voltage, and the third voltage.

20. An SRAM memory comprising:

a plurality of SRAM cells, each SRAM cell comprising a pair of cross-coupled invertors configured to store a bit-value, the invertors being connected between a local ground node and a local supply node, each invertor being connected via its input to one of a pair of complementary bitlines via one of a pair of access transistors for writing the bit-value in the SRAM cell, the pair of access transistors being controllable by a write_wordline;

means for applying a global ground voltage and a global supply voltage to the SRAM memory;

means for precharging one of the bitlines of the pair of complementary bitlines of the SRAM cell to the global ground voltage, and for precharging the other bitline of the pair of complementary bitlines to a complementary voltage, depending on the bit-value to be written in the SRAM cell;

means for applying a first voltage to the local ground node, the first voltage having a value higher than the value of the global ground voltage by a first predefined amount;

means for applying a second voltage to the write_wordline for enabling its pair of access transistors, the second voltage having a value higher than the value of the global supply voltage by a second predefined amount; and

means for applying a third voltage to the local supply node, the third voltage having a value higher than the value of the global supply voltage by a third predefined amount.