Abstract: A microelectronic component. The microelectronic component includes a metallic conductor on a first dielectric layer, wherein the metallic conductor has a polygonal, in particular rectangular, cross-section, and the metallic conductor has a region with a corner, wherein the corner faces away from the first dielectric layer. At least one second layer with a second permittivity and a second conductivity is arranged on the region with the corner, and a fourth layer with a fourth permittivity and a fourth conductivity is arranged on the second layer, The second permittivity has a higher value than the fourth permittivity and the second conductivity has a higher value than the fourth conductivity.

Abstract: A trench transistor. The transistor including: a semiconductor region, a trench structure formed in the semiconductor region; a gate insulation layer and an electrically conductive gate layer formed on the gate insulation layer in the trench structure, and a gate contact, which is electrically conductively connected to the gate layer in an edge area of the trench transistor. A thickness of the gate insulation layer in the edge area of the trench transistor is greater than in an active area of the trench transistor.

Abstract: A semiconductor component, in particular a transistor. The semiconductor component includes: source and drain layers doped according to a first type, a channel layer located vertically between the source layer doped and the drain layer, and a gate trench, which extends vertically from the source layer to the drain layer and adjoins the channel layer and at least a portion of the source layer. A first shielding region doped according to a second type, extends vertically from the source layer, or a semiconductor surface adjoining it, to the drain layer, and a second shielding region doped according to the second type, is arranged vertically below a bottom of the gate trench, wherein the gate trench and the second shielding region are designed such that, in one or more delimited regions, the second shielding region extends horizontally at least to the first shielding region.

Abstract: A power transistor cell including a layer arrangement, which includes a front side and a rear side, the front side being situated opposite the rear side. A trench extends starting from, and perpendicular to, the front side along a first direction into the layer arrangement. The trench extends at least into a current-spreading layer, and expands along a second direction, which is situated perpendicularly to the first direction. Field shielding areas are situated at least partially in the current-spreading layer, wherein source areas and field shielding contacting areas are situated alternatingly along the second direction. One portion each of the body areas is situated between each source area and each field shielding contacting area. The field shielding contacting areas connect the field shielding areas to first metal areas on the front side. The field shielding contacting areas make contact at least partially with side faces of the trench.

Abstract: A vertical semiconductor component. The component includes: a drift region having a first conductivity type; a trench structure on or above the drift region, a shielding structure situated laterally next to at least one sidewall of the trench structure on or above the drift region and having a second conductivity type, and the shielding structure having at least a part of a shielding structure-trench structure such that the shielding structure has at least a first region having a first thickness and a second region having a second thickness, and an edge termination structure on or above the drift region and having the second conductivity type, and the shielding structure having a first doping degree, and the edge termination structure having a second doping degree; and at least in the second region of the shielding structure, the edge termination structure being situated between the drift region and the shielding structure.

Abstract: A vertical fin field-effect transistor. The transistor has a semiconductor fin, an n-doped source region, an n-doped drift region, an n-doped channel region in the semiconductor fin situated vertically between the source region and the drift region, a gate region horizontally adjacent to the channel region, a gate dielectric electrically insulating the gate region from the channel region, a boundary surface between the gate dielectric and the channel region having negative boundary surface charges, a p-doped gate shielding region situated below the gate region so that, given the vertical projection, the gate shielding region is situated within a surface limited by the gate dielectric, a source contact electrically conductively connected to the source region, and an electrically conductive region between the gate region and the p-doped gate shielding region. The p-doped gate shielding region is electrically conductively connected to the source contact by the electrically conductive region.

Abstract: A method for monitoring an oil-injected screw compressor configured to compress aspirated air by returning oil from an oil separator vessel (11) to a compression chamber (12) of a compressor block (30), for condensate formation in the oil circuit due to a too low compression discharge temperature (VET), determines a water inlet mass flow {acute over (m)}ein(t) and a water outlet mass flow {acute over (m)}aus (t) for a point in time t and determines generated condensate flow ?{acute over (m)}w (t)={acute over (m)}ein(t)?{acute over (m)}aus (t) on the basis of difference formation.

Abstract: A method for monitoring an oil-injected screw compressor configured to compress aspirated air by returning oil from an oil separator vessel (11) to a compression chamber (12) of a compressor block (30), for condensate formation in the oil circuit due to a too low compression discharge temperature (VET), determines a water inlet mass flow {dot over (m)}ein(t) and a water outlet mass flow {dot over (m)}aus(t) for a point in time t and determines generated condensate flow ?{dot over (m)}w(t)={dot over (m)}ein(t)?{dot over (m)}aus(t) on the basis of difference formation.

Abstract: A trench transistor. The transistor including: a semiconductor region, a trench structure formed in the semiconductor region; a gate insulation layer and an electrically conductive gate layer formed on the gate insulation layer in the trench structure, and a gate contact, which is electrically conductively connected to the gate layer in an edge area of the trench transistor. A thickness of the gate insulation layer in the edge area of the trench transistor is greater than in an active area of the trench transistor.

Abstract: A power transistor cell including a layer arrangement, which includes a front side and a rear side, the front side being situated opposite the rear side. A trench extends starting from, and perpendicular to, the front side along a first direction into the layer arrangement. The trench extends at least into a current-spreading layer, and expands along a second direction, which is situated perpendicularly to the first direction. Field shielding areas are situated at least partially in the current-spreading layer, wherein source areas and field shielding contacting areas are situated alternatingly along the second direction. One portion each of the body areas is situated between each source area and each field shielding contacting area. The field shielding contacting areas connect the field shielding areas to first metal areas on the front side. The field shielding contacting areas make contact at least partially with side faces of the trench.

Abstract: A semiconductor device. The semiconductor device includes a drift region of a first conductivity type, a channel region of a second conductivity type on the drift region, a source region of the first conductivity type on the channel region, a trench, which forms an insulated gate and extends through the source region and the channel region so that its bottom is situated in the drift region, and at least one buried region of the second conductivity type, which extends within the drift region from an edge region of the drift region to the trench and is in direct contact with a first subarea of a surface of the trench, a second subarea of a surface of the trench being in direct contact with the drift region, and the buried region being connected to the source region in an electrically conducting manner.

Abstract: A method for manufacturing a power transistor. The method includes: applying a first epitaxial layer including a first doping concentration to a front side of a semiconductor substrate, producing an expansion layer, which is situated inside the first epitaxial layer, producing various implanted areas starting from the front side of the semiconductor substrate, producing a trench structure starting from the front side of the semiconductor substrate, producing first isolation areas in the surroundings of the trench structure, producing transistor heads, and applying metal layers.

Abstract: A transistor cell including a semiconductor substrate, which has a front side and a rear side, the front side being situated opposite the rear side. An epitaxial layer is situated on the front side. Channel regions are situated on the epitaxial layer. Source regions are situated on the channel regions. A trench and field shielding regions extending from the front side of the semiconductor substrate into the epitaxial layer, the field shielding regions each being situated laterally spaced apart from the trench and the trench having a shallower depth than the field shielding regions. An implanted expansion region having a particular thickness is situated below the trench.

Abstract: A semiconductor component. The semiconductor component includes a semiconductor substrate that includes a first side, on which an epitaxial layer is situated. On the epitaxial layer, body regions are sectionally situated, and on the body regions, source regions are situated. A plurality of first trenches and a plurality of second trenches extending starting from the source regions into the epitaxial layer. The first trenches have a greater depth than the second trenches. A second trench sectionally extends into a first trench in each case. On a trench surface of the first trenches, a layer including a first doping is situated in each case. The first trenches are filled with a first material including a second doping, the first doping having a higher value than the second doping.

Abstract: A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.

Abstract: A vertical power transistor, including a semiconductor substrate, on which at least one first layer and one second layer are situated, the second layer being situated on the first layer, and the first layer including a first semiconductor material; and a plurality of trenches, which extend from an upper side of the second layer into the first layer. The first layer has a first doping, and each trench has a first region, which extends from the respective trench bottom to a first level. Each first region is filled with a second semiconductor material, which has a second doping. The first semiconductor material and the second semiconductor material are different. Each first region is connected electrically to the second layer. The second doping is higher than the first doping. Heterojunctions, which behave as unipolar, rectifying junctions, form between the first layer and each first region.

Abstract: A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.

Abstract: A vertical power transistor including a semiconductor substrate, which has a front side on which at least one epitaxial layer, one channel layer, and one source layer are situated. The epitaxial layer includes a first semiconductor material which has a first doping, and a plurality of first trenches and second trenches, the first trenches and the second trenches being situated alternatingly and extending perpendicularly at least into the channel layer starting from a surface of the source layer, an area extending perpendicularly into the epitaxial layer, starting from an underside of each first trench bottom, the area including a second semiconductor material which encompasses a second doping.

Abstract: A semiconductor system includes a PIN diode including a heavily n-doped layer, a lightly n-doped layer situated on the heavily n-doped layer, and a p-doped layer situated on the lightly n-doped layer, the p-doped layer forming an ohmic contact with a first metallization and the heavily n-doped layer forming an ohmic contact with a second metallization. During operation in the forward direction, a high injection takes place in which the lightly n-doped layer is flooded with charge carriers. At least two trench structures are introduced into the lightly n-doped layer, the trench structures on a surface in contact with the n-doped surface including a dielectric layer. The surface of the lightly n-doped layer in contact with the dielectric layer includes an increased surface recombination velocity for charge carriers.

Abstract: A method for monitoring an oil-injected screw compressor configured to compress aspirated air by returning oil from an oil separator vessel (11) to a compression chamber (12) of a compressor block (30), for condensate formation in the oil circuit due to a too low compression discharge temperature (VET), determines a water inlet mass flow {dot over (m)}ein(t) and a water outlet mass flow {dot over (m)}aus(t) for a point in time t and determines generated condensate flow ?{dot over (m)}w(t)={dot over (m)}ein(t)?{dot over (m)}aus(t) on the basis of difference formation.