Abstract: Embodiments of the present invention provides methods, computer program products, and a system for processing hierarchical references for a formal equivalence check. In certain embodiments, hierarchical references of a first design are identified as functionally equivalent to hierarchical references of a second design. Value outputs of the first design can be compared to the value outputs of the second design to determine whether the value outputs of the respective designs match.

Abstract: Embodiments of the present invention provides methods, computer program products, and a system for processing hierarchical references for a formal equivalence check. In certain embodiments, hierarchical references of a first design are identified as functionally equivalent to hierarchical references of a second design. Value outputs of the first design can be compared to the value outputs of the second design to determine whether the value outputs of the respective designs match.

Abstract: An embodiment relates to a method of manufacturing an insulated gate bipolar transistor in a semiconductor body. A first field stop zone portion of a first conductivity type is formed on a semiconductor substrate. A second field stop zone portion of the first conductivity type is formed on the first field stop zone portion. A drift zone of the first conductivity type is formed on the second field stop zone portion. A doping concentration in the drift zone is smaller than 1013 cm?3 along a vertical extension of more than 30% of a thickness of the semiconductor body upon completion of the insulated gate bipolar transistor.

Abstract: A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.

Abstract: A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.

Abstract: A circuit may comprise an electronic switching element, an integrated sensor, and a low-impedance path from one of the terminals of the sensor to one of the terminals of the electronic switching element.

Abstract: A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.

Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.

Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.

Abstract: A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.

Abstract: A circuit may comprise an electronic switching element, an integrated sensor, and a low-impedance path from one of the terminals of the sensor to one of the terminals of the electronic switching element.

Abstract: A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region.

Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.

Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.

Abstract: An IGBT includes a semiconductor substrate, a source metallization and an emitter metallization. The semiconductor substrate includes a source region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and an emitter region of the second conductivity type. The source metallization is in contact with the source region. The emitter metallization is in contact with the emitter region. The emitter region includes a first doping region of the second conductivity type forming an ohmic contact with the emitter metallization and a second doping region of the second conductivity type forming a non-ohmic contact with the emitter metallization.

Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

Abstract: One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

Abstract: A logic design and synthesis program, method and system provides intelligibility and independence of separate blocks in digital logic designs at the synthesis level. The sequential and combinational logic are separated and the sequential logic is then mapped to flip-flop library components. State-retaining elements, i.e., flip-flops detected in the input hardware description language (HDL) are represented in the sequential logic HDL output. The combinational logic HDL and the sequential logic HDL are connected only by signals, so signals are introduced to represent the flip-flop signals and variables detected in the input HDL. The sequential and combinational logic HDL are then synthesized to produce the design.

Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

Abstract: The signal state that a signal of interest within a system under test has during each of a plurality of cycles of operation of the system under test is stored in a trace file. In association with the signal state, information regarding a requested access to the signal state by a control program during a particular cycle among the plurality of cycles is also stored. From the trace files a presentation is generated that presents, for at least a signal of interest within the system under test, a plurality of signal state indications, each indicating a respective state that the signal had during a one of a plurality of cycles of operation of the system under test. The presentation also indicates, in a graphically distinctive manner, at least one cycle of operation during which a control program requested access to a state of the signal, so that the influence of the control program on the state of the system under test is visually apparent.