Patents by Inventor Won-chang Jung
Won-chang Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240114414Abstract: Provided are a method and apparatus for providing a network switching service to a user equipment.Type: ApplicationFiled: October 4, 2023Publication date: April 4, 2024Applicant: KT CORPORATIONInventors: Ji-Young JUNG, Kun-Woo PARK, Se-Hoon KIM, Il-Yong KIM, Sang-Hyun PARK, Ho-Jun JANG, Won-Chang CHO
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Publication number: 20240106794Abstract: Provided are a method and apparatus for a user equipment, a core network, and a second device to enable bidirectional communication for second devices. The method of the second device may include receiving internet protocol (IP) configuration information for automatically configuring an IP version 6 (IPv6) address of the second device from a core network through a user equipment; generating the IPv6 address using information in the IP configuration information; and transmitting the generated IPv6 address to the core network through the UE.Type: ApplicationFiled: September 6, 2023Publication date: March 28, 2024Applicant: KT CORPORATIONInventors: Won-Chang CHO, Se-Hoon KIM, Il-Yong KIM, Kun-Woo PARK, Sang-Hyun PARK, Ho-Jun JANG, Ji-Young JUNG
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Publication number: 20240098022Abstract: Provided are a method and apparatus for providing a multi virtual local area network service to user equipments.Type: ApplicationFiled: September 19, 2023Publication date: March 21, 2024Applicant: KT CORPORATIONInventors: Ho-Jun JANG, Se-Hoon KIM, Won-Chang CHO, Sang-Hyun PARK, Kun-Woo PARK, Ji-Young JUNG
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Patent number: 8644101Abstract: A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line, and a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal.Type: GrantFiled: January 30, 2012Date of Patent: February 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: In-Woo Jun, Won-Chang Jung
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Publication number: 20120195146Abstract: A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line, and a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal.Type: ApplicationFiled: January 30, 2012Publication date: August 2, 2012Inventors: In-Woo JUN, Won-Chang JUNG
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Patent number: 8010765Abstract: In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.Type: GrantFiled: July 10, 2007Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Sun Choi, Won-Chang Jung, Hi-Choon Lee, Sung-Min Yim, Chul-Woo Park, Won-Il Bae
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Patent number: 7692995Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: GrantFiled: December 19, 2008Date of Patent: April 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Patent number: 7609580Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: GrantFiled: December 19, 2008Date of Patent: October 27, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Patent number: 7606090Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: GrantFiled: December 19, 2008Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Publication number: 20090116319Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: ApplicationFiled: December 19, 2008Publication date: May 7, 2009Inventors: Jeong-Sik Nam, Sang -Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Publication number: 20090116327Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: ApplicationFiled: December 19, 2008Publication date: May 7, 2009Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Patent number: 7477565Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: GrantFiled: October 30, 2007Date of Patent: January 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Patent number: 7460418Abstract: A semiconductor memory device and a read data skew control method thereof, in which a point of time when read data is output can he controlled using pad bonding in stack packages. The semiconductor memory device includes a bonding option pad and a delay control circuit that controls the point of time when data is output from an output buffer depending on logic states of a signal applied to the bonding option pad. Thus, when using the semiconductor memory device in stack packages, the read data skew generated as a result of a load on a bonding wire can be compensated by connecting the bonding option pad to ground voltage or a supply voltage.Type: GrantFiled: May 10, 2007Date of Patent: December 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Won-chang Jung, Hi-choon Lee
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Publication number: 20080056034Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: ApplicationFiled: October 30, 2007Publication date: March 6, 2008Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Publication number: 20080052482Abstract: In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.Type: ApplicationFiled: July 10, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joo-Sun CHOI, Won-Chang JUNG, Hi-Choon LEE, Sung-Min YIM, Chul-Woo PARK, Won-Il BAE
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Publication number: 20080043548Abstract: A semiconductor memory device and a read data skew control method thereof, in which a point of time when read data is output can he controlled using pad bonding in stack packages. The semiconductor memory device includes a bonding option pad and a delay control circuit that controls the point of time when data is output from an output buffer depending on logic states of a signal applied to the bonding option pad. Thus, when using the semiconductor memory device in stack packages, the read data skew generated as a result of a load on a bonding wire can be compensated by connecting the bonding option pad to ground voltage or a supply voltage.Type: ApplicationFiled: May 10, 2007Publication date: February 21, 2008Inventors: Won-chang Jung, Hi-choon Lee
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Patent number: 7307910Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: GrantFiled: June 30, 2005Date of Patent: December 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung
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Patent number: 7248085Abstract: An internal reset signal generator that generates an internal reset disable signal after an internal high voltage device has been completely reset. This can substantially reduce errors in operation of semiconductor memory devices. A first circuit generates a first control signal until the power source voltage reaches a stabilized state and a second control signal thereafter. A delay circuit responds to the first and second control signals and a reset complete signal from a reset circuit, and generates an internal reset disable signal only when the second control signal and the reset completion signal are inputted simultaneously, and in other cases, generates an internal reset signal. A reset circuit is connected in a feedback circuit with the delay circuit. It resets a high-voltage device in response to the internal reset signal, and generates a reset completion signal when the high voltage device is reset.Type: GrantFiled: May 17, 2005Date of Patent: July 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Won-Chang Jung
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Patent number: 6992905Abstract: A high voltage generation circuit comprises a first boosting unit, a second boosting unit, a delay circuit which delays the output of the first boosting unit as applied the second boosting unit, a pre-charge unit, and switch units which connect respective nodes in response to control signals. A voltage supply circuit is also provided that converts an externally supplied power source voltage (VCC) to a predetermined pre-charge voltage (VPP2).Type: GrantFiled: July 8, 2004Date of Patent: January 31, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Won-chang Jung
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Publication number: 20060002204Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.Type: ApplicationFiled: June 30, 2005Publication date: January 5, 2006Inventors: Jeong-Sik Nam, Sang-Kyun Park, Kwang-Hyun Kim, Byung-Sik Moon, Won-Chang Jung