Abstract: Phase change memory devices and methods of making phase changeable memory devices including a heating electrode disposed on a substrate are provided. The heating electrode includes an electrode hole in the heating electrode. A phase change material pattern is provided in the electrode hole and contacts a sidewall of the electrode hole. In some embodiments, the electrode hole extends through the heating electrode. In some embodiments, the phase changeable material pattern only contacts the electrode at a sidewall of the electrode hole.

Abstract: An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction.

Abstract: Phase change Random Access Memory (PRAM) devices include a substrate and a phase change layer pattern on the substrate. The phase change layer pattern includes a sharp tip and at least one wall that extends from the sharp tip in a direction away from the substrate. At least one contact hole node is provided that contacts the phase change material pattern adjacent the sharp tip.

Abstract: Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

Abstract: A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line.

Abstract: Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

Abstract: A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.

Abstract: Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer extending between the bit line and the magnetic flux focusing layer. This electrically insulating layer may contact an upper surface of the magnetic flux focusing layer and a lower surface of the bit line. The magnetic memory cell further includes a non-ferromagnetic electrically conductive layer extending between the magnetic flux focusing layer and the magnetic storage element. The electrically insulating layer is configured to cause current passing in a first direction (e.g.

Abstract: Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

Abstract: Methods may be provided for operating a magnetic random access memory (MRAM device including a magnetic tunnel junction structure and a heat generating layer. More particularly, a write current may be provided through the magnetic tunnel junction structure and through the heat generating layer, and the write current may have a magnitude sufficient to change a program state of the magnetic tunnel junction structure. Related devices are also discussed.

Abstract: A magnetic random access memory (MRAM) device may include a magnetic tunnel junction structure between first and second electrodes. Methods of operating such as MRAM device may include providing a write current through the first electrode, through the magnetic tunnel junction structure, and through the second electrode. An auxiliary switching magnetic field may be generated by the write current through the first electrode, and a portion of the auxiliary switching magnetic field may pass through the magnetic tunnel junction structure in a direction perpendicular to a direction of the write current through the magnetic tunnel junction structure. Moreover, a magnitude of the write current and/or the auxiliary switching magnetic field may be sufficient to change a program state of the magnetic tunnel junction structure. Related devices and structures are also discussed.

Abstract: A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent a sidewall of the magnetic tunnel junction structure and may be configured to provide a magnetic field through the magnetic tunnel junction structure. Related methods of operating magnetic random access memory devices are also discussed.

Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

Abstract: A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent a sidewall of the magnetic tunnel junction structure and may be configured to provide a magnetic field through the magnetic tunnel junction structure. Related methods of operating magnetic random access memory devices are also discussed.

Abstract: Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer extending between the bit line and the magnetic flux focusing layer. This electrically insulating layer may contact an upper surface of the magnetic flux focusing layer and a lower surface of the bit line. The magnetic memory cell further includes a non-ferromagnetic electrically conductive layer extending between the magnetic flux focusing layer and the magnetic storage element. The electrically insulating layer is configured to cause current passing in a first direction (e.g.

Abstract: Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.

Abstract: Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer extending between the bit line and the magnetic flux focusing layer. This electrically insulating layer may contact an upper surface of the magnetic flux focusing layer and a lower surface of the bit line. The magnetic memory cell further includes a non-ferromagnetic electrically conductive layer extending between the magnetic flux focusing layer and the magnetic storage element. The electrically insulating layer is configured to cause current passing in a first direction (e.g.

Abstract: A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional area. A second contact is connected to a second region of the chalcogenide element and having a second cross-sectional area. A first programmable volume of the chalcogenide material is defined in the first region of the chalcogenide element, a state of the first programmable volume being programmable according to a resistance associated with the first contact. A second programmable volume of the chalcogenide material is defined in the second region of the chalcogenide element, a state of the second programmable volume being programmable according to a second resistance associated with the second contact.

Abstract: A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.

Abstract: A PRAM and method of forming the same are disclosed. In various embodiments, the PRAM includes a lower insulation layer formed on a semiconductor substrate, a phase change material pattern formed on the lower insulation layer and a heating electrode contacting the phase change material pattern. The heating electrode can be formed of a material having a positive temperature coefficient such that specific resistance of the material increases as a function of temperature.