Abstract: Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.

Abstract: Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

Abstract: Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

Abstract: In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

Abstract: Information is read from a magnetic tunnel junction (MTJ) of a magnetic memory. An electromagnetic field is applied to the MTJ that is sufficient to cause a change in the electrical resistance of the MTJ. The change in the electrical resistance of the MTJ is at least substantially removed responsive to removal of the applied electromagnetic field. The change in the electrical resistance of the MTJ that associated with the application of the electromagnetic field is measured. The information in the MTJ is determined based on the measured change in the electrical resistance of the MTJ. The MTJ can be determined to store a representation of a first binary value when the electrical resistance of the MTJ decreases, and to store a representation of a second binary value when the electrical resistance increases.

Abstract: A method of forming a memory device may include forming an insulating layer on a substrate, and forming a first electrode through at least a portion of the insulating layer. A memory storage element may be formed on the first electrode so that the first electrode is between the memory storage element and the substrate, and a second electrode may be formed on the memory storage element so that the memory storage element is between the first and second electrodes. After forming the memory storage element and after forming the second electrode, insulating spacers may be formed on sidewalls of the memory storage element. After forming the insulating spacers, an interconnection line may be formed on the second electrode, on the insulating spacers, and on the insulating layer beyond the insulating spacers. Related memory devices are also discussed.

Abstract: Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer extending between the bit line and the magnetic flux focusing layer. This electrically insulating layer may contact an upper surface of the magnetic flux focusing layer and a lower surface of the bit line. The magnetic memory cell further includes a non-ferromagnetic electrically conductive layer extending between the magnetic flux focusing layer and the magnetic storage element. The electrically insulating layer is configured to cause current passing in a first direction (e.g.

Abstract: A memory device with a magnetic field generator and method of operating and manufacturing the same. In the device and method, a magnetic memory may includes a magnetic tunneling junction (MTJ) cell, a transistor, and a bit line, and a magnetic field generator external to the magnetic memory to generate a global magnetic field toward the magnetic memory in a parallel direction to the bit line.

Abstract: A magnetic random access memory device may include a first electrode on a substrate, a magnetic tunneling junction element electrically connected to the electrode, and a second electrode electrically connected to the first electrode through the magnetic tunneling junction element. In addition, a heat generating layer may be electrically connected in series between the first and second electrodes, and the heat generating layer may provide a relatively high resistance with respect to electrical current flow. Related methods are also discussed.

Abstract: An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction.

Abstract: A magnetic memory includes digit lines, bit lines, and magnetic tunnel junctions (MTJs) that are between the bits lines and the digit lines. The digit lines intersect the bit lines at an oblique angle. The digit lines may intersect the bit lines at an oblique angle of from 15° to 75°.

Abstract: A magnetic memory device includes bottom electrodes disposed on an interlayer dielectric on a substrate. The bottom electrodes are spaced apart from one another in one direction as much as a first distance. A planarized insulation layer fills spaces between the bottom electrodes and has a top surface coplanar with a top surface of the bottom electrode. Magnetic tunnel junction (MTJ) patterns are connected to the bottom electrodes, respectively, and are spaced apart from one another in the one direction as much as a second distance. The first distance is equal to the second distance.

Abstract: A method of reading data stored in a data storage element of an integrated circuit memory device may include applying a first electrical signal to the data storage element, and while applying the first electrical signal, taking a first measurement of an electrical characteristic of the data storage element. After taking the first measurement of the electrical characteristic, a second electrical signal may be applied to the data storage element with the first and second electrical signals being different. While applying the second electrical signal, a second measurement of the electrical characteristic of the data storage element may be taken, and the first and second measurements of the electrical characteristic of the data storage element may be compared to determine a state of the data stored in the data storage element. Related devices are also discussed.

Abstract: A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent a sidewall of the magnetic tunnel junction structure and may be configured to provide a magnetic field through the magnetic tunnel junction structure. Related methods of operating magnetic random access memory devices are also discussed.

Abstract: A magnetic random access memory (MRAM) device may include a magnetic tunnel junction structure between first and second electrodes. Methods of operating such as MRAM device may include providing a write current through the first electrode, through the magnetic tunnel junction structure, and through the second electrode. An auxiliary switching magnetic field may be generated by the write current through the first electrode, and a portion of the auxiliary switching magnetic field may pass through the magnetic tunnel junction structure in a direction perpendicular to a direction of the write current through the magnetic tunnel junction structure. Moreover, a magnitude of the write current and/or the auxiliary switching magnetic field may be sufficient to change a program state of the magnetic tunnel junction structure. Related devices and structures are also discussed.

Abstract: Methods may be provided for operating a magnetic random access memory (MRAM device including a magnetic tunnel junction structure and a heat generating layer. More particularly, a write current may be provided through the magnetic tunnel junction structure and through the heat generating layer, and the write current may have a magnitude sufficient to change a program state of the magnetic tunnel junction structure. Related devices are also discussed.

Abstract: Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

Abstract: Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.

Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

Abstract: A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line.