Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.

Abstract: Methods of operating field emission displays are disclosed. In one embodiment, a method for operating a field emission display includes applying a voltage to an extraction grid with respect to an emitter in proximity to the extraction grid to extract electrons from the emitter, regulating a supply of electrons from the emitter in response to a control signal, and accelerating the electrons from the emitter towards a faceplate with an accelerating voltage that also reverse biases a semiconductor diode extending from a baseplate that includes the extraction grid and the emitter to the faceplate.

Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.

Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.

Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.

Abstract: A display includes a baseplate and an emitter formed on the baseplate. The display also includes a faceplate having a cathodoluminescent coating on a surface facing the baseplate and the emitter. A plurality of spacers separate the faceplate and the baseplate to prevent bowing of the faceplate or the baseplate towards each other. The spacers are formed from silicon, simplifying field emission device assembly and resulting in a superior display.

Abstract: Methods of manufacturing faceplates for field emission displays are disclosed. In one embodiment, a method for manufacturing a faceplate includes forming a transparent conductive layer on a transparent viewing screen, forming an insulating layer on the transparent conductive layer, anodically bonding silicon to the insulating layer, directionally etching the silicon to form isolated regions of silicon on the insulating layer, and etching the insulating layer using the isolated regions of silicon as a mask.

Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.

Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.

Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as a anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.

Abstract: A display includes a baseplate and an emitter formed on the baseplate. The display also includes a faceplate having a cathodoluminescent coating on a surface facing the baseplate and the emitter. A plurality of spacers separate the faceplate and the baseplate to prevent bowing of the faceplate or the baseplate towards each other. The spacers are formed from silicon, simplifying field emission device assembly and resulting in a superior display.

Abstract: A display includes a baseplate and an emitter formed on the baseplate. The display also includes a faceplate having a cathodoluminescent coating on a surface facing the baseplate and the emitter. A plurality of spacers separate the faceplate and the baseplate to prevent bowing of the faceplate or the baseplate towards each other. The spacers are formed from silicon, simplifying field emission device assembly and resulting in a superior display.

Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.

Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.

Abstract: Methods of fabricating a liquid crystal display element on a substrate includes forming a thin film transistor on the substrate, the thin film transistor including a gate electrode covered by a channel region and a gate pad conductively connected to the gate electrode. A pad electrode is formed on the substrate, spaced apart from the gate pad. A portion of the gate pad and a portion of the pad electrode are exposed, and the exposed portion of the gate pad selectively plated to thereby form a conductive barrier layer on the exposed portion of the gate pad. A pixel electrode is then formed contacting the conductive barrier layer and the exposed portion of the pad electrode to thereby connect the gate pad and the pad electrode. Preferably, the selective plating includes electroless plating the exposed portion of the gate pad to thereby form the conductive barrier layer.

Abstract: The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.