Abstract: Provided are relatively higher-performance wire-type semiconductor devices and relatively economical methods of fabricating the same. A wire-type semiconductor device may include at least one pair of support pillars protruding above a semiconductor substrate, at least one fin protruding above the semiconductor substrate and having ends connected to the at least one pair of support pillars, at least one semiconductor wire having ends connected to the at least one pair of support pillars and being separated from the at least one fin, a common gate electrode surrounding the surface of the at least one semiconductor wire, and a gate insulating layer between the at least one semiconductor wire and the common gate electrode.

Abstract: The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.

Abstract: A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode on at least portions of outer side surfaces of the at least one pair of fins and extending onto top portions of the at least one pair of fins on an angle with the at least one pair of fins. The non-volatile memory device may further include at least one pair of gate insulating layers between the at least one control gate electrode and the at least one pair of fins, and at least one pair of storage node layers between the at least one pair of gate insulating layers and at least a portion of the at least one control gate electrode. The at least one control gate electrode may extend onto top portions of the at least one pair of fins in a zigzag fashion.

Abstract: Off-axis projection optics that includes first and second mirrors positioned off-axis and sharing a confocal point that are arranged to reduce linear astigmatism. If a distance between an object plane and the first mirror is l1, an incident angle of light coming from the object plane to the first mirror is i1, a distance between the first mirror and the confocal point is l1?, a distance between the confocal point and the second mirror is l2, an incident angle of light coming from the first mirror to the second mirror is i2, and a distance between the second mirror and an image plane is l2?, the off-axis projection optics may satisfy the following equation: l 1 ? + l 1 l 1 ? tan ? ? ? i 1 = l 2 ? + l 2 l 2 ? tan ? ? ? i 2 .

Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

Abstract: Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Abstract: A memory device may include a plurality of resistance nodes. The resistance nodes may be connected serially in a NAND or AND structure, by a plurality of metal plugs. The metal plugs may have a lower resistance. A control device corresponding to each resistance node may control the resistance devices. Each control device may be connected to a bit line and a word line. The bit line may be connected to the metal plugs via a corresponding switch device.

Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same may be provided. The semiconductor memory device may include a substrate, at least a pair of fins protruding from the semiconductor substrate and facing each other with a gap between fins of the pair of fins, an insulating layer formed between the pair of the fins, a storage node formed on the pair of fins and/or a surface of a portion of the insulating layer, and/or a gate electrode formed on the storage node.

Abstract: Off-axis projection optics that includes first and second mirrors positioned off-axis and sharing a confocal point that are arranged to reduce linear astigmatism. If a distance between an object plane and the first mirror is l1, an incident angle of light coming from the object plane to the first mirror is i1, a distance between the first mirror and the confocal point is l1?, a distance between the confocal point and the second mirror is l2, an incident angle of light coming from the first mirror to the second mirror is i2, and a distance between the second mirror and an image plane is l2?, the off-axis projection optics may satisfy the following equation: l 1 ? + l 1 l 1 ? tan ? ? i 1 = l 2 ? + l 2 l 2 ? tan ? ? i 2 .

Abstract: Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Abstract: A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line, respectively. Each of the first string and the second string have a string selection transistors, a plurality of unit devices and a source selection transistor. Word lines are respectively connected to control gates of the unit devices in the same rows. A first string selection line and a second string selection line are respectively connected to the gates of the string selection transistors of the first string and the second string. A first source selection line and a second source selection line are respectively connected to the gates of the first string and the second string.

Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.

Abstract: Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.

Abstract: A multi-bit non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins protruding above the body. A first insulation layer may be formed on the body between the at least one pair of fins. A plurality of pairs of control gate electrodes may extend across the first insulation layer and the at least one pair of fins, and may at least partly cover upper portions of outer walls of the at least one pair of fins. A plurality of storage nodes may be formed between the control gate electrodes and the at least one pair of fins, and may be insulated from the substrate. A first distance between adjacent pairs of control gate electrodes may be greater than a second distance between control gate electrodes in each pair.

Abstract: Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner.

Abstract: Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.

Abstract: Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.

Abstract: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

Abstract: A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.