Abstract: A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair of fins protruding from a body and extending, spaced from each other along one direction, as at least one pair of channel regions. At least one control gate electrode may be formed across the channel regions, and at least one pair of storage nodes may be interposed in at least one portion between the control gate electrode and the channel regions.

Abstract: A fin FET CMOS device, a method of manufacturing the same, and a memory including the fin FET CMOS device are provided. The CMOS device may include a substrate, an n-type transistor disposed on the substrate, an interlayer insulating layer disposed on the n-type transistor, and a p-type transistor disposed on the interlayer insulating layer. The n-type transistor and the p-type transistor may have a common gate insulating layer and a fin gate.

Abstract: A photomask and method thereof. In an example method, a photomask may be manufactured by forming an oxide layer on a surface, patterning the oxide layer to form an oxide pattern, the oxide pattern including a plurality of oxide pattern bodies and a plurality of oxide windows, filling the plurality of oxide windows with an absorbent to form an absorbent pattern and reducing the plurality of oxide pattern bodies. An example photomask may include an oxide pattern-based absorbent pattern including a plurality of absorbent pattern bodies and a plurality of absorbent pattern windows.

Abstract: A metal line structure of an optical scanner and a method of fabricating the same are provided. The metal line structure of the optical scanner includes: a glass substrate having a metal line region etched to a predetermined depth; a metal line formed in the metal line region; a diffusion barrier layer that is formed on the glass substrate and covers the metal line; and an optical scanner structure combined with the glass substrate.

Abstract: A memory device may include a plurality of resistance nodes. The resistance nodes may be connected serially in a NAND or AND structure, by a plurality of metal plugs. The metal plugs may have a lower resistance. A control device corresponding to each resistance node may control the resistance devices. Each control device may be connected to a bit line and a word line. The bit line may be connected to the metal plugs via a corresponding switch device.

Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.

Abstract: Off-axis projection optics that includes first and second mirrors positioned off-axis and sharing a confocal point that are arranged to reduce linear astigmatism. If a distance between an object plane and the first mirror is l1, an incident angle of light coming from the object plane to the first mirror is i1, a distance between the first mirror and the confocal point is l1?, a distance between the confocal point and the second mirror is l2, an incident angle of light coming from the first mirror to the second mirror is i2, and a distance between the second mirror and an image plane is l2?, the off-axis projection optics may satisfy the following equation: l 1 ? + l 1 l 1 ? tan ? ? ? i 1 = l 2 ? + l 2 l 2 ? tan ? ? ? i 2 .

Abstract: A hybrid multi-bit memory device may include a plurality of unit cells arranged in a matrix of a plurality of rows and columns. Each of the unit cells may include a first memory unit and a second memory unit. The first and second memory unit may share a source and a drain. The first memory unit of each unit cell arranged in each row may be connected to one of a plurality of word lines, and the drain of each unit cell arranged in each column may be connected to one of a plurality of bit lines.

Abstract: A memory device may include a first memory unit and a second memory unit. The first memory unit may include a first storage node storing data using a first method. The second memory unit may include a second storage node using a second method. The second method may be different than the first method, and the first memory unit and the second memory unit may share a source and a drain.

Abstract: A photomask may include a reflection layer including a material capable of reflecting electromagnetic radiation, and at least one ion region. The ion region may be formed by implanting ions of an absorbent capable of absorbing electromagnetic radiation. The reflection layer may have a stack structure including a plurality of layers. The ions of the dopant may be implanted into at least one of the plurality of layers.

Abstract: A mask for lithography and a method of manufacturing the same. The mask may include a substrate, a reflection layer formed of a material capable of reflecting electromagnetic rays on the substrate and an absorption pattern formed in a desired pattern such that absorbing regions with respect to electromagnetic rays and windows through which electromagnetic rays pass are formed, wherein the absorption pattern includes at least one side surface that is adjacent to the window and is inclined with respect to the reflection layer. The method may include forming a reflection layer which is formed of a material capable of reflecting electromagnetic rays on a substrate, forming an absorption layer which is formed of a material capable of absorbing electromagnetic rays on the refection layer, and patterning the absorption layer to form an absorption pattern with at least one side surface adjacent to a window that has an inclined side surface with respect to the reflection layer.

Abstract: A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask.

Abstract: A multi bits flash memory device and a method of operating the same are disclosed.

Abstract: Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.

Abstract: A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the exposed portions of the semiconductor substrate to form source and drain regions, wherein the gate stack structure is etched such that its width increases from top to bottom. Accordingly, it is possible to manufacture a memory device with high integration, using a simplified manufacture process.

Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.

Abstract: Methods of operating field emission displays are disclosed. In one embodiment, a method for operating a field emission display includes applying a voltage to an extraction grid with respect to an emitter in proximity to the extraction grid to extract electrons from the emitter, regulating a supply of electrons from the emitter in response to a control signal, and accelerating the electrons from the emitter towards a faceplate with an accelerating voltage that also reverse biases a semiconductor diode extending from a baseplate that includes the extraction grid and the emitter to the faceplate.

Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.

Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.