Abstract: A device, apparatus and method for performing a Fast Fourier Transform (FFT). The Fast Fourier Transform (FFT) processing device includes a coefficient generator, a memory, and an accumulator. The coefficient generator is configured to generate a first set of coefficient values from one or more twiddle factor coefficients. The memory stores the first set of coefficient values. The accumulator receives and accumulates one or more coefficient values from the first set of coefficient values, the accumulator generating one or more output values based on the accumulated one or more coefficient values.

Abstract: A stacked semiconductor package and a method for assembling the same are disclosed, the stacked semiconductor package including a semiconductor chip having a plurality of wire bonding pads thereon; leads formed in a direction to electrically connect with the wire bonding pads; a heat sink connected to the predetermined wire bonding pad to radiate out heat of the semiconductor chip; and an epoxy supporting and protecting the semiconductor chip, the leads, and the heat sink.

Abstract: A method for manufacturing a semiconductor package in which production time and cost are reduced and production yield is increased is disclosed, including the steps of: providing a backer having a groove, a cap of the backer, a semiconductor chip having a bonding pad, and a lead frame; coating a binder on an edge portion of the recess of the backer and an edge portion of the cap of the backer; mounting the semiconductor chip on the recess of the backer; forming a conductive material on an edge portion of a lead in the lead frame and contacting the lead having the conductive material thereon with the bonding pad of the semiconductor chip; contacting the backer and the cap; and trimming and forming the lead frame.

Abstract: Method for manufacturing a T-gate useful for reducing a gate resistance, improving through-put, and simplifying an MMIC (monolithic microwave integrated circuit) process is disclosed, the method including the steps of depositing a first photoresist layer on a semiconductor substrate and patterning the first photoresist layer so as to expose a predetermined portion of the surface of the substrate; successively forming a seed metal layer and a second photoresist layer on the entire surface inclusive of the exposed substrate and patterning the second photoresist layer so as to define a gate electrode region; plating Au on the seed metal layer on the gate electrode region so as to form a gate electrode; and removing the first and second photoresist layers and the seed metal layer except the gate electrode.