Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first network node may receive second phase tracking reference signal (PTRS) configuration information for a second PTRS that is associated with a second network node. The first network node may transmit a physical downlink shared channel (PDSCH) that includes a first PTRS that is based at least in part on first PTRS configuration information, the PDSCH being based at least in part on cross-PTRS rate matching and the second PTRS configuration information. Numerous other aspects are described.

Abstract: A display device includes: a first substrate having a first surface, a second surface opposite to the first surface, and a first side surface extending between the first surface and the second surface, the first substrate comprises a rigid material; a second substrate on the first surface of the first substrate and including a flexible material, the second substrate covering at least a part of the first side surface of the first substrate; and an emission material layer on the second substrate and including a plurality of light-emitting elements.

Abstract: A display device and method of manufacturing a display device. The display device includes a first electrode, a second electrode facing the first electrode, a first insulating layer on the first electrode and the second electrode and between the first electrode and the second electrode, a light emitting element on the first insulating layer, a second insulating layer covering the light emitting element and exposing end portions of the light emitting element, a third insulating layer on the second insulating layer, a first contact electrode electrically connected to the first electrode, on the third insulating layer and in contact with a first end portion of the light emitting element exposed by the second insulating layer, and a second contact electrode electrically connected to the second electrode, on the third insulating layer and in contact with a second end portion of the light emitting element exposed by the second insulating layer.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit an indication of a UE capability for a physical downlink shared channel (PDSCH) channel estimation for a subband full duplex (SBFD) operation. The UE may demodulate a PDSCH scheduled based at least in part on the UE capability. Numerous other aspects are described.

Abstract: A method for wireless communication at a transmitting wireless device and related apparatus are provided. In the method, the device determines, based on the first parameter associated with a Forward Error Correction (FEC) process and a second parameter associated with a probabilistic shaping process, the transport block (TB) size for a TB associated with a signal to be transmitted, and performs the probabilistic shaping process on a first set of data bits of the signal on the TB to obtain a second set of transmit bits. The TB cyclic redundancy check (CRC) is inserted into the TB before or after the probabilistic shaping process, and the probabilistic shaping process is applied on the TB level across multiple code blocks (CBs) associated with the TB or on the CB level individually inside each CB of the multiple CBs. The device further transmits the signal using the second set of transmit bits.

Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

Abstract: A display device including a first substrate including a first area, a second area and a bending area between the first area and the second area; a display element layer disposed on the first area of the first substrate; multiple signal lines disposed on the bending area of the first substrate, the signal lines being spaced apart from one another in a first direction and electrically connected to the display element layer; and a bending protection layer disposed on the bending area of the first substrate and covering the signal lines, wherein the bending protection layer includes a first portion and a second portion, the first portion has an inclined surface, the second portion having an approximately flat surface, the second portion overlapping the signal lines including outermost signal lines, the first portion not overlapping the signal lines.

Abstract: A light emitting device includes first and second electrodes disposed on a substrate; an insulating layer disposed on the substrate and including a groove extending in a first direction intersecting with the first and the second electrodes, and first and second contact portions that expose areas of the first and the second electrodes; light emitting elements disposed in the groove between the first and the second electrodes, each including first and second ends electrically connected to the first and second electrodes, respectively; a first contact electrode electrically connected to the light emitting elements on the first ends, and electrically connected to the first electrode on the first contact portion; and a second contact electrode electrically connected to the light emitting elements on the second ends, and electrically connected to the second electrode on the second contact portion.

Abstract: A display device includes: a substrate comprising an open portion; a pad portion on the substrate and exposed through the open portion; a fanout line integrally formed with the pad portion; a data line electrically connected to the fanout line; a flexible film under the substrate and comprising a lead electrode inserted into the open portion of the substrate to directly contact the pad portion; and a contact portion covering a lower surface of the lead electrode and a lower surface of the pad portion to electrically connect the lead electrode and the pad portion.

Abstract: A semiconductor memory device with improved integration and electrical characteristics. The semiconductor memory device includes a peri-gate structure, a first peri-connecting structure on the peri-gate structure, a data storage pattern on the first peri-connecting structure, an active pattern that includes a first surface and a second surface opposite to each other in a first direction, and a first side wall and a second side wall opposite to each other in a second direction, the first surface of the active pattern connected to the data storage pattern and facing a substrate, a bit line on the active pattern, connected to the second surface of the active pattern, and extends in the second direction, a word line on the first side wall of the active pattern and extending in a third direction, a second peri-connecting structure connected to the bit line and a connecting pad connected to the second peri-connecting wiring.

Abstract: Methods, systems, and devices for wireless communications are described. A transmitting device may filter data tones (e.g., in edge subbands of an allocated frequency band) to achieve time domain windowing or shaping. Data tones of edge subbands of a configured frequency band may be filtered to shape a waveform such that it does not extend beyond symbol boundaries (e.g., does not result in emission leakage). In some examples, the transmitter may provide an indication of subband frequency domain shaping filters used to the receiver, to support demodulation on the receiver side. In some examples, the transmitter may indicate a demodulation reference signal (DMRS) comb structure (e.g., of the edge subbands) to the receiver, and the receiver may determine or estimate the filters of the subband frequency domain shaping based on the comb structure or the indication of the filters.

Abstract: A semiconductor device includes a lower substrate, a memory cell structure including a wordline on the lower substrate, a bitline disposed on the lower substrate and intersecting the wordline, and a cell capacitor connected to the lower substrate, an upper substrate having a back side adjacent to the lower substrate and a front side opposite to the back side, a circuit element disposed on the front side of the upper substrate and overlapping the memory cell structure in a vertical direction, and a through via penetrating the upper substrate and electrically connecting the memory cell structure and the circuit element with each other.

Abstract: Provided are a display device and a manufacturing method thereof. The display device comprises: a substrate; a first electrode and a second electrode disposed on the substrate to be spaced apart from each other; a first insulating layer disposed on the substrate so as to cover at least a portion of the first electrode and the second electrode; and at least one first light emitting element disposed between the first electrode and the second electrode, on the first insulating layer. The first insulating layer comprises: a first sub-insulating layer comprising a first portion including a hydrophilic material and a second portion which is a region of the first insulating layer except for the first portion and includes a hydrophobic material; and a second sub-insulating layer disposed below the first sub-insulating layer, and at least a portion of the at least one first light emitting element is disposed on the first portion.

Abstract: Methods, systems, and devices for wireless communications are described. A scheduled entity transmits an indication of frequency resources that have different transmission requirements from those of other frequency resources in a smallest frequency domain scheduling unit that comprises the frequency resources for the scheduled entity. The scheduled entity receives, from a scheduling entity, signaling indicating at least one characteristic of how a channel is to be scheduled on the frequency resources from a scheduling entity. The scheduled entity communicates with the scheduling entity in accordance with the at least one characteristic.

Abstract: A semiconductor memory device includes a peri-gate structure on a substrate, a first bonding pad on the peri-gate structure, a shielding conductive pattern on the first bonding pad, a second bonding pad between the shielding conductive pattern and the first bonding pad and contacting the first bonding pad, a bit line on the shielding conductive pattern extending in a first direction, an active pattern on the bit line and including a lower surface and an upper surface, and a first side wall and a second side wall opposite to each other in the first direction, the lower surface of the active pattern being connected to the bit line, a word line on the first side wall of the active pattern, and extends in a third direction, and a data storage pattern on the active pattern, and is connected to the upper surface of the active pattern.

Abstract: A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.

Abstract: A display device and a method of manufacturing a display device are provided.

Abstract: A light emitting device includes first and second electrodes disposed on a substrate; an insulating layer disposed on the substrate and including a groove extending in a first direction intersecting with the first and the second electrodes, and first and second contact portions that expose areas of the first and the second electrodes; light emitting elements disposed in the groove between the first and the second electrodes, each including first and second ends electrically connected to the first and second electrodes, respectively; a first contact electrode electrically connected to the light emitting elements on the first ends, and electrically connected to the first electrode on the first contact portion; and a second contact electrode electrically connected to the light emitting elements on the second ends, and electrically connected to the second electrode on the second contact portion.

Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

Abstract: A battery pack includes a lower case defining a first space having a predetermined size; an upper case at an upper part of the lower case to be fastened to the lower case, the upper case defining a second space; at least one module frame in the first space of the lower case and the second space of the upper case, the module frame defining a battery cell receiving recess; and a battery cell in the battery cell receiving recess. An impact attenuation member configured to protect the module frame from external impact is disposed between an outer surface of the module frame and an inner surface of the lower case.