Abstract: Provided are an artificial intelligence (AI) agent device and a computer-implemented method. The AI agent device includes: an arbiter engine that decomposes input information into pieces of single atomic information composed of keywords and connection status; a query augmentation engine configured to perform a retrieval in a knowledge base on the basis of the single atomic information input from the arbiter engine, combine information of the single atomic information and information retrieved from the knowledge base, and transmit a query to an AI system; and a retrieval and analysis engine configured to receive results of the AI system decomposed into pieces of single atomic information from the arbiter engine, perform a retrieval in the knowledge base on the basis of keywords and connection status, and determine whether each of the decomposed results of the AI system is deliverable to a user.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A semiconductor device includes first to third semiconductor chips consecutively stacked. The first semiconductor chip comprises a first semiconductor substrate. A circuit layer is on a top surface of the first semiconductor substrate. First pads are on a top surface of the circuit layer. The first pads are electrically connected to the circuit layer. The second semiconductor chip comprises a second semiconductor substrate. Passive devices are in the second semiconductor substrate. Second pads are on a bottom surface of the second semiconductor substrate. The second pads are electrically connected to the passive devices. Third pads are on a top surface of the second semiconductor substrate. The third semiconductor chip comprises fourth pads on a bottom surface of the third semiconductor chip. The first pads and the second pads are directly connected to each other. The third pads and the fourth pads are directly connected to each other.

Abstract: Disclosed is a semiconductor package including a semiconductor chip that includes a chip pad on one surface of the semiconductor chip, a redistribution pattern on the one surface of the semiconductor chip and electrically connected to the chip pad, and a photosensitive dielectric layer between the semiconductor chip and the redistribution pattern. The photosensitive dielectric layer may be in physical contact with the redistribution pattern. The redistribution pattern includes a signal redistribution pattern, a ground redistribution pattern, and a power redistribution pattern. A vertical distance between the chip pad and the signal redistribution pattern may be greater than a width of the signal redistribution pattern.

Abstract: A semiconductor structure may include an interposer die, a slave die, a plurality of first connection members and a plurality of second connection members. The interposer die may include a first surface and a second surface that is an opposite surface of the first surface. The slave die may include a third surface and a fourth surface that is an opposite surface of the third surface, and a plurality of through-silicon vias. The plurality of first connection members may be disposed on the first surface. The plurality of second connection members may electrically connect the second surface and the third surface.

Abstract: A semiconductor package is provided. The semiconductor package comprises a first semiconductor chip including the first signal wiring structure disposed in an upper surface thereof, and a first power wiring structure disposed in a lower surface thereof, a second semiconductor chip disposed on the first signal wiring structure and including a second signal wiring structure, a second power wiring structure disposed on the second semiconductor chip and a first power connection pillar connecting the first power wiring structure and the second power wiring structure to each other.

Abstract: A semiconductor package includes a power delivery network, a semiconductor chip on a top surface of the power delivery network, and having first and second surfaces opposite to each other, a second semiconductor chip on the top surface horizontally spaced from the first semiconductor chip, the second semiconductor chip having third surface and fourth surfaces, opposite to each other, chip stacks on the first semiconductor chip, and on the second semiconductor chip. The first surface is an active surface. The third surface is an active surface of the second semiconductor chip. The first chip stack includes third semiconductor chips on the first surface of the first semiconductor chip. The third semiconductor chips is disposed such that an active surface thereof faces the first semiconductor chip, and the first chip stack and the second semiconductor chip may be electrically connected to each other through the power delivery network.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A semiconductor package including a buffer structure including a first redistribution layer, a first buffer chip on the first redistribution layer, a second redistribution layer on the first buffer chip, and a first molding layer filling between the first redistribution layer and the second redistribution layer, and a first chip stack and a first semiconductor chip on the buffer structure and spaced apart from each other, wherein the first buffer chip overlaps at least a portion of the first semiconductor chip in a first direction from the buffer structure toward the first semiconductor chip, may be provided.

Abstract: Disclosed is a semiconductor package including a semiconductor chip that includes a chip pad on one surface of the semiconductor chip, a redistribution pattern on the one surface of the semiconductor chip and electrically connected to the chip pad, and a photosensitive dielectric layer between the semiconductor chip and the redistribution pattern. The photosensitive dielectric layer may be in physical contact with the redistribution pattern. The redistribution pattern includes a signal redistribution pattern, a ground redistribution pattern, and a power redistribution pattern. A vertical distance between the chip pad and the signal redistribution pattern may be greater than a width of the signal redistribution pattern.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Abstract: A semiconductor package includes a first interconnect substrate on a first redistribution substrate and having a first opening penetrating the first interconnect substrate. A first semiconductor chip is on the first redistribution substrate and the first opening of the first interconnect substrate. A second redistribution substrate is on the first interconnect substrate and the first semiconductor chip. A second interconnect substrate is on the second redistribution substrate and has a second opening penetrating the second interconnect substrate. A second semiconductor chip is on the second redistribution substrate and in the second opening of the second interconnect substrate.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Abstract: A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.