Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.

Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.

Abstract: A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.

Abstract: An electric cooker is configured to cook food in a pressurized state and a non-pressurized state of an inner pot, thereby improving the cooking quality and convenience of use. The electric cooker includes a main body having an inner pot configured to accommodate food and a heating unit; a lid coupled to an upper portion of the main body and opened/closed by an opening/closing unit; and a pressure switching selection unit arranged to pass through the lid and configured to switch or maintain opened/closed states to discharge internal steam from the inner pot by interworking with the opening/closing unit.

Abstract: An electric cooker is configured to cook in a pressure state and a non-pressure state of an inner pot, thereby improving the cooking quality and convenience of use. The electric cooker includes a main body configured to accommodate an inner pot; a lid coupled to an upper portion of the main body and having a handle portion provided at one side of an upper portion of the lid to interwork with an inner pot locking unit configured to lock the inner pot; a pressure switching unit arranged to pass through the lid and configured to switch or maintain an opened or closed state to discharge internal steam from the inner pot according to a rotation of the handle portion; and a pressure-responsive operating unit which is selectively opened or closed according to a pressure inside the inner pot in a pressure cooking mode in which the pressure switching unit is closed.

Abstract: An electric cooker is configured to cook in a pressure state and a non-pressure state of an inner pot, thereby improving the cooking quality and convenience of use.

Abstract: A semiconductor package includes a first interconnect substrate on a first redistribution substrate and having a first opening penetrating the first interconnect substrate. A first semiconductor chip is on the first redistribution substrate and the first opening of the first interconnect substrate. A second redistribution substrate is on the first interconnect substrate and the first semiconductor chip. A second interconnect substrate is on the second redistribution substrate and has a second opening penetrating the second interconnect substrate. A second semiconductor chip is on the second redistribution substrate and in the second opening of the second interconnect substrate.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.

Abstract: To enable a user to cook both in a pressure state and in a non-pressure state inside the inner pot and thus improve cooking quality and ease of use, the present invention provides an electric cooker including a main body in which an inner pot for accommodating food is installed; a lid coupled to the main body to be opened or closed, in which a passthrough portion is formed; a pressure converter communicating with the passthrough portion, in which a selectively opened/closed state for discharging steam inside the inner pot is maintained; and a pressure-responsive actuators communicating with the passthrough portion and selectively opened/closed depending on a pressure level inside the inner pot in a pressure cooking mode.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: In a method for communication between hosts using a peripheral component interconnect express (PCIe) dedicated communication module, a PCIe dedicated communication module of a first host generates a first connection buffer for receiving a connection command from a second host, stands by a connection request from the second host, determines whether the first host is connectable to the second host in response to the connection request received from the second host, and, if it is determined that the first host is connectable to the second host, generates a first connection socket connected to the second host for the purpose of data communication. The PCIe dedicated communication module generates a first communication buffer to store data received from the second host, assigns the first communication buffer to the first connection socket, permits the connection between the first and second hosts, and stands by data communication with the second host.

Abstract: A heat radiation-thermoelectric fin includes a thermoelectric inorganic material on a heterogeneous laminate of graphene. The heterogeneous laminate may be tube-shaped or plate-shaped, and a metal conductor may be coupled to one or more of the heterogeneous laminate. A thermoelectric module may be formed to include the fin, and a thermoelectric apparatus may include a heat supplier connected to the thermoelectric module.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: A thermoelectric material includes a stack structure including alternately stacked first and second material layers. The first material layer may include a carbon nano-material. The second material layer may include a thermoelectric inorganic material. The first material layer may include a thermoelectric inorganic material in addition to the carbon nano-material. The carbon nano-material may include, for example, graphene. At least one of the first and second material layers may include a plurality of nanoparticles. The thermoelectric material may further include at least one conductor extending in an out-of-plane direction of the stack structure.

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.