Patents by Inventor Woo-jin Jang
Woo-jin Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117405Abstract: The present invention relates to a colorimetric biosensor, preparation method thereof, and antibiotic susceptibility testing method using the same, and more specifically, in the present invention, it is possible to prepare a colorimetric biosensor comprising a porous hydrogel structure including polydiacetylene and a hydrogel polymer (alginate, PEG-DA, etc.); and a microbial nutrient source, and it may be applied to a colorimetric biosensor for detecting microorganisms or a method for testing antibiotic susceptibility of microorganisms for allowing in real-time measurement and exhibiting excellent sensitivity using the colorimetric biosensor.Type: ApplicationFiled: December 21, 2022Publication date: April 11, 2024Inventors: Tae Joon Jeon, Sun Min Kim, Hui Soo Jang, Woo Jin Jeong, Seo Yoon Song
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Publication number: 20230099844Abstract: Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.Type: ApplicationFiled: June 2, 2022Publication date: March 30, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ho KIM, Woo Jin JANG, Jeong Hoon AHN, Yun Ki CHOI
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Patent number: 11018685Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.Type: GrantFiled: May 14, 2020Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Jin Jang, Yong Lim, Seung Hyun Oh, Jae Hoon Lee
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Publication number: 20210091782Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.Type: ApplicationFiled: May 14, 2020Publication date: March 25, 2021Inventors: Woo Jin Jang, Yong Lim, Seung Hyun Oh, Jae Hoon Lee
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Patent number: 10720447Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: GrantFiled: July 16, 2019Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Publication number: 20190341400Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Patent number: 10411034Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: GrantFiled: June 7, 2018Date of Patent: September 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Patent number: 10359799Abstract: A bandgap reference voltage generation system includes a common mode voltage generator, a bandgap reference voltage generation circuit, and a switch controller. The bandgap reference voltage generation circuit includes a plurality of transistors having source terminals respectively connected to drain terminals of a plurality of PMOS transistors. The switch controller provides a ground voltage to the bandgap reference voltage generation circuit in a first mode and a common mode voltage to the bandgap reference voltage generation circuit in a second mode. The bandgap reference voltage generation circuit causes the plurality of the transistors to operate in a linear region by providing the common mode voltage to gate electrodes of the plurality of the transistors in the first mode and a saturation region by providing the ground voltage to the gate electrodes of the plurality of the transistors in the second mode.Type: GrantFiled: March 7, 2018Date of Patent: July 23, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Jin Jang, Seung Hyun Oh, Jong Woo Lee
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Patent number: 10303197Abstract: A reference voltage circuit is provided. The reference voltage circuit includes a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, and an amplifier configured to output a reference voltage having same value as the second voltage. The plurality of NMOS transistors include a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected to the first node, and the plurality of NMOS transistors are connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node.Type: GrantFiled: January 12, 2018Date of Patent: May 28, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-hyun Oh, Woo-jin Jang, Jong-woo Lee
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Publication number: 20190157293Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: ApplicationFiled: June 7, 2018Publication date: May 23, 2019Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Publication number: 20190079553Abstract: A bandgap reference voltage generation system includes a common mode voltage generator, a bandgap reference voltage generation circuit, and a switch controller. The bandgap reference voltage generation circuit includes a plurality of transistors having source terminals respectively connected to drain terminals of a plurality of PMOS transistors. The switch controller provides a ground voltage to the bandgap reference voltage generation circuit in a first mode and a common mode voltage to the bandgap reference voltage generation circuit in a second mode. The bandgap reference voltage generation circuit causes the plurality of the transistors to operate in a linear region by providing the common mode voltage to gate electrodes of the plurality of the transistors in the first mode and a saturation region by providing the ground voltage to the gate electrodes of the plurality of the transistors in the second mode.Type: ApplicationFiled: March 7, 2018Publication date: March 14, 2019Inventors: Woo Jin JANG, Seung Hyun OH, Jong Woo LEE
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Patent number: 10195638Abstract: Provided are an apparatus and method for coating a separator. The method includes supplying a coating solution to a receiving chamber; applying the coating solution received in the receiving chamber to a surface of the separator through a coating bar; collecting coating solution overflowing the receiving chamber by a collection chamber surrounding the receiving chamber; and returning coating solution from the collection chamber to the receiving chamber through a return line.Type: GrantFiled: October 29, 2014Date of Patent: February 5, 2019Assignee: SAMSUNG SDI CO., LTD.Inventors: Woo Jin Jang, Yun Gi Kim, Jin Kyu Park, Sang Ho Lee
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Publication number: 20190025867Abstract: A reference voltage circuit is provided. The reference voltage circuit includes a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, and an amplifier configured to output a reference voltage having same value as the second voltage. The plurality of NMOS transistors include a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected to the first node, and the plurality of NMOS transistors are connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node.Type: ApplicationFiled: January 12, 2018Publication date: January 24, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-hyun Oh, Woo-jin Jang, Jong-woo Lee
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Patent number: 9900020Abstract: A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.Type: GrantFiled: April 21, 2017Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-kwon Kim, Jong-woo Lee, Yang-hun Lee, Woo-jin Jang
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Publication number: 20170331487Abstract: A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.Type: ApplicationFiled: April 21, 2017Publication date: November 16, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-kwon KIM, Jong-woo LEE, Yang-hun LEE, Woo-jin JANG
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Patent number: 9500407Abstract: A drying apparatus that dries a porous membrane that is carryable along a predetermined direction and a drying method, the drying apparatus including a housing; a plurality of air suppliers arranged in the housing along the predetermined direction so as to inject air toward the porous membrane; and a plurality of air exhausters arranged in the housing along the predetermined direction so as to exhaust air that has been injected from the air suppliers to an exterior of the housing, wherein the plurality of air suppliers are symmetrically arranged with one another at opposite sides of the porous membrane to face each other with the porous membrane disposable therebetween.Type: GrantFiled: September 24, 2014Date of Patent: November 22, 2016Assignee: Samsung SDI Co., Ltd.Inventors: Woo Jin Jang, Tae Sik Kim, Jin Kyu Park, Hun Young Park, Jun Ho Chung, Bong Hyun Cho
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Patent number: 9281240Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.Type: GrantFiled: March 2, 2015Date of Patent: March 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Jeong Moon, Woo-Choel Noh, Woo-Jin Jang, Hun Kim, Hong-Jae Shin
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Publication number: 20150255336Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.Type: ApplicationFiled: March 2, 2015Publication date: September 10, 2015Inventors: Hyo-Jeong Moon, Woo-Cheol Noh, Woo-Jin Jang, Hun Kim, Hong-Jae Shin
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Publication number: 20150118389Abstract: Provided are an apparatus and method for coating a separator. The method includes supplying a coating solution to a receiving chamber; applying the coating solution received in the receiving chamber to a surface of the separator through a coating bar; collecting coating solution overflowing the receiving chamber by a collection chamber surrounding the receiving chamber; and returning coating solution from the collection chamber to the receiving chamber through a return line.Type: ApplicationFiled: October 29, 2014Publication date: April 30, 2015Inventors: Woo Jin JANG, Yun Gi KIM, Jin Kyu PARK, Sang Ho LEE
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Publication number: 20150089831Abstract: A drying apparatus that dries a porous membrane that is carryable along a predetermined direction and a drying method, the drying apparatus including a housing; a plurality of air suppliers arranged in the housing along the predetermined direction so as to inject air toward the porous membrane; and a plurality of air exhausters arranged in the housing along the predetermined direction so as to exhaust air that has been injected from the air suppliers to an exterior of the housing, wherein the plurality of air suppliers are symmetrically arranged with one another at opposite sides of the porous membrane to face each other with the porous membrane disposable therebetween.Type: ApplicationFiled: September 24, 2014Publication date: April 2, 2015Inventors: Woo Jin JANG, Tae Sik KIM, Jin Kyu PARK, Hun Young PARK, Jun Ho CHUNG, Bong Hyun CHO