Patents by Inventor Wookyung You
Wookyung You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136254Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.Type: ApplicationFiled: May 18, 2023Publication date: April 25, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Sangkoo KANG, Wookyung YOU, Minjae KANG, Koungmin RYU, Hoonseok SEO, Woojin LEE, Junchae LEE
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Patent number: 11948883Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.Type: GrantFiled: April 2, 2021Date of Patent: April 2, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seonghun Lim, Wookyung You, Kyoungwoo Lee, Juyoung Jung, Il Sup Kim, Chin Kim, Kyoungpil Park, Jinhyung Park
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Publication number: 20240096797Abstract: Disclosed is a semiconductor device including a substrate, conductive structures on the substrate and extending in parallel to each other in a first direction, and a first interlayer dielectric layer in first and second trenches between the conductive structures. A width in a second direction of the first trench may be less than a width in the second direction of the second trench. The first interlayer dielectric layer may include a lower interlayer dielectric layer and an upper interlayer dielectric layer on the lower interlayer dielectric layer, sequentially stacked. A mechanical strength of the upper interlayer dielectric layer may be greater than a mechanical strength of the lower interlayer dielectric layer.Type: ApplicationFiled: June 7, 2023Publication date: March 21, 2024Inventors: MINJAE KANG, YEONGGIL KIM, WOOKYUNG YOU, WOOJIN LEE, JAYEONG HEO
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Publication number: 20240085812Abstract: A substrate processing apparatus includes a chamber having an internal space configured to process a substrate loaded therein; a light source configured to emit light on the substrate to harden a photoresist pattern coated on the substrate; and a transparent division part provided between the substrate and the light source, wherein the transparent division part divides the chamber into a first space, in which the light source is provided, and a second space, in which the substrate is provided.Type: ApplicationFiled: August 4, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyuhee Han, Koungmin Ryu, Kyeongbeom Park, Jongmin Baek, Wookyung You, Woojin Lee, Juhee Lee
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Publication number: 20240030127Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: ApplicationFiled: August 9, 2023Publication date: January 25, 2024Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Patent number: 11776906Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.Type: GrantFiled: September 21, 2021Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jangho Lee, Jongmin Baek, Wookyung You, Kyu-Hee Han, Suhyun Bark
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Patent number: 11764149Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: GrantFiled: July 18, 2022Date of Patent: September 19, 2023Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Patent number: 11646263Abstract: A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.Type: GrantFiled: January 22, 2021Date of Patent: May 9, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wookyung You, Kyeongbeom Park, Sungbin Park, Suhyun Park, Jongmin Baek, Jangho Lee, Seonghun Lim, Deokyoung Jung, Kyuhee Han
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Publication number: 20230059177Abstract: A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.Type: ApplicationFiled: April 14, 2022Publication date: February 23, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Sangshin JANG, Wookyung YOU, Sangkoo KANG, Donghyun ROH, Koungmin RYU, Jongmin BAEK
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Publication number: 20220359379Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: ApplicationFiled: July 18, 2022Publication date: November 10, 2022Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Patent number: 11424182Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: GrantFiled: December 22, 2020Date of Patent: August 23, 2022Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Publication number: 20220068810Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.Type: ApplicationFiled: April 2, 2021Publication date: March 3, 2022Inventors: Seonghun LIM, Wookyung YOU, Kyoungwoo LEE, Juyoung JUNG, Il Sup KIM, Chin KIM, Kyoungpil PARK, Jinhyung PARK
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Publication number: 20220005763Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jangho LEE, Jongmin BAEK, Wookyung YOU, Kyu-Hee HAN, Suhyun BARK
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Publication number: 20210391254Abstract: A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.Type: ApplicationFiled: January 22, 2021Publication date: December 16, 2021Inventors: Wookyung You, Kyeongbeom Park, Sungbin Park, Suhyun Park, Jongmin Baek, Jangho Lee, Seonghun Lim, Deokyoung Jung, Kyuhee Han
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Publication number: 20210351123Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: ApplicationFiled: December 22, 2020Publication date: November 11, 2021Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Patent number: 11139244Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.Type: GrantFiled: February 18, 2020Date of Patent: October 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jangho Lee, Jongmin Baek, Wookyung You, Kyu-Hee Han, Suhyun Bark
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Patent number: 11133249Abstract: A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.Type: GrantFiled: May 18, 2020Date of Patent: September 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeonggil Kim, Jongmin Baek, Wookyung You, Kyuhee Han
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Publication number: 20210043561Abstract: A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.Type: ApplicationFiled: May 18, 2020Publication date: February 11, 2021Inventors: YEONGGIL KIM, Jongmin Baek, Wookyung You, Kyuhee Han
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Publication number: 20210005551Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.Type: ApplicationFiled: February 18, 2020Publication date: January 7, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jangho LEE, Jongmin Baek, Wookyung YOU, Kyu-Hee HAN, Suhyun Bark
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Patent number: 10875091Abstract: A method for manufacturing metal powder is provided. The method includes preparing first metal powder, agglomerating the first metal powder to manufacture second metal powder in which the first metal powder is agglomerated, coating the second metal powder with an organic binder, and agglomerating and coarsening the second metal powder coated with the organic binder to manufacture third metal powder having higher flowability than the second metal powder coated with the organic binder.Type: GrantFiled: April 1, 2015Date of Patent: December 29, 2020Assignees: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION, HANYANG UNIVERSITY ERICA CAMPUSInventors: Jaisung Lee, Wookyung You