Abstract: A display device includes a display panel including a plurality of pixels, a data driver configured to provide data voltages to the pixels, and a gate driver configured to provide gate signals to the pixels. The display device also includes a controller configured to control the data driver and the gate driver, and to control the magnitude of a sensing initialization voltage applied to the pixels based on a frame rate value when operating in a variable frame mode.

Abstract: A display device includes a display unit which includes pixels, an emission driver which applies an emission control signal for allowing the pixels to emit light, and a signal controller which receives a data enable signal including an active period and a blank period during which an image signal is inputted and outputs a control signal for controlling the emission driver such that an emission period of the pixels is changed in response to a blank period.

Abstract: A display device includes a display panel, a data driver, a gate driver, and a controller. The display panel includes a plurality of pixels. The data driver provides data voltages to the plurality of pixels through data lines during an active period of a frame period and provides a blank voltage to the plurality of pixels through the data lines during a blank period of the frame period. The gate driver provides a gate-on voltage to the plurality of pixels through gate lines during the active period and provides a gate-off voltage to the plurality of pixels through the gate lines during the blank period. The controller controls the data driver and the gate driver. The blank voltage increases and the gate-off voltage increases, when a time in the blank period reaches a predetermined time.

Abstract: A gate driving circuit includes: a plurality of driving stages, each driving stage configured to provide a gate signal to a corresponding gate line among a plurality of gate lines, wherein each of the plurality of driving stages includes: a first transistor electrically connected between a first clock terminal and a gate output terminal, the first transistor including a gate electrode electrically connected to a first node, the first clock terminal to receive a first clock signal; a second transistor configured to transmit a first carry signal to the first node; and a third transistor electrically connected between the first node and a first voltage terminal, the third transistor including a gate electrode electrically connected to the first voltage terminal, the first voltage terminal to receive a first voltage, wherein the gate output terminal is electrically connected to the corresponding gate line.

Abstract: A method for in-vitro tissue cultivation. The method may include providing a seeded-scaffold to a scaffold holder suspended in a medium contained in a bioreactor chamber. The method may further include rotating, via a rotation mechanism which the bioreactor chamber is coupled to, the bioreactor chamber about two orthogonal axes based on a predetermined motion cycle as a stimulation for tissue growth. The method may further include applying, via a stimulator coupled to the bioreactor chamber, at least one other stimulation for tissue growth to the seeded-scaffold. An apparatus for in-vitro tissue cultivation.

Abstract: A display device includes a display panel, a data driver, a gate driver, and a controller. The display panel includes a plurality of pixels. The data driver provides data voltages to the plurality of pixels through data lines during an active period of a frame period and provides a blank voltage to the plurality of pixels through the data lines during a blank period of the frame period. The gate driver provides a gate-on voltage to the plurality of pixels through gate lines during the active period and provides a gate-off voltage to the plurality of pixels through the gate lines during the blank period. The controller controls the data driver and the gate driver. The blank voltage increases and the gate-off voltage increases, when a time in the blank period reaches a predetermined time.

Abstract: Disclosed is a plasma torch with a structure capable of performing reversed polarity/straight polarity operation, wherein the plasma torch is coupled to a melter and melts a waste material such as radioactive waste or industrial waste by generating and sustaining a plasma arc between electrodes, the plasma torch including: a rear electrode provided inside a torch pipe and electrically connected to become one of an anode and a cathode; and a front electrode provided at a front end of the torch pipe at a position adjacent to a front end of the rear electrode and electrically connected to become a remaining one of the anode and the cathode, wherein electrical connections of the rear and front electrodes are switchable with each other so that the plasma torch operates as a reversed polarity plasma torch or a straight polarity plasma torch.

Abstract: A display device may include a backlight unit, a display panel, and a backlight driver, and a panel driver. The backlight unit may include light source blocks including a first light source block. The display panel may include dimming regions including a first dimming region and respectively overlapping the light source blocks. The first dimming region may overlap the first light source block. The backlight driver may control a turn-on period and a turn-off period of each of the light source blocks. The panel driver may sequentially provide scan signals to the dimming regions for controlling light transmission of the dimming regions. A turn-off period of the first light source block may start before a scan period of the first dimming region and may end after the scan period of the first dimming region. The first dimming region may receive corresponding scan signals in the scan period.

Abstract: A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

Abstract: A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.

Abstract: The present invention relates to a plasma furnace capable of separating and discharging different kinds of molten material, which comprises a furnace body 110; and a heating portion 140 for heating the lateral discharge gate 120, 130, wherein the furnace body comprises a melt discharge portion formed through a lower portion of the melting chamber 101 provided for accommodating molten material; and at least two lateral discharge gates 120, 130 provided at different heights capable of discharging molten material.

Abstract: The present invention relates to a plasma furnace which can efficiently treat various types of waste in large amounts. The plasma furnace comprises a melting chamber 101 for accommodating a melt, an upper surface forming the upper portion of the melting chamber 101 with a horizontal upper surface 111 and an inclined upper surface 112 having a slope with respect to the horizontal upper surface 111, a melt discharge portion 130 formed through a bottom surface of the melting chamber for discharging molten material therethrough, and an input apparatus 120 having a slope for inputting waste into the melting chamber 101, and the mixed type plasma torch 191, 192 provided on the inclined upper surface 112 with a slope for generating melting heat in the melting chamber 101.

Abstract: A display device includes a display panel including gate lines, data lines, and pixels individually connected to a corresponding gate line and data line, a gate driver driving the gate lines, a data driver driving the data lines, and a driving controller. The driving controller receives, from an external source, first image signals and a variable frequency signal indicating an operation frequency (frame rate) for the display device. The driving controller converts the first image signals to second image signals by adding a compensation value corresponding to the operation frequency to the first image signals, and outputs the second image signals to the data driver. Embodiments may compensate for luminance reduction/variation and reduce image artifacts that otherwise occur due to variable frequency operation. An alternative embodiment dynamically controls an amount of light output from a backlight according to the variable frequency signal.

Abstract: A display device includes a display panel which includes gate lines and data lines, a gate driver electrically connected to the gate lines, a temperature sensor which includes at least three temperature sensing circuits which are disposed adjacent to the gate driver, and a voltage generating circuit which outputs a test voltage to each of the temperature sensing circuits and outputs a clock signal, which is compensated based on a result voltage having a lowest voltage level among result voltages provided from the temperature sensing circuits, to the gate driver.

Abstract: A display apparatus includes a display panel, a data driving circuit, and a gate driving circuit. The display panel is configured to display an image and includes a gate line and a data line. The data driving circuit is configured to output a data signal to the data line. The gate driving circuit is configured to output a gate signal to the gate line and to control a kick-back time of the gate signal according to a temperature of the display panel. The kick-back time is a time when the gate signal is decreased from a gate on voltage to a kick-back voltage that is between the gate on voltage and a gate off voltage.

Abstract: A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.

Abstract: A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

Abstract: A display device includes a display panel including gate lines, data lines, and pixels individually connected to a corresponding gate line and data line, a gate driver driving the gate lines, a data driver driving the data lines, and a driving controller. The driving controller receives, from an external source, first image signals and a variable frequency signal indicating an operation frequency (frame rate) for the display device. The driving controller converts the first image signals to second image signals by adding a compensation value corresponding to the operation frequency to the first image signals, and outputs the second image signals to the data driver. Embodiments may compensate for luminance reduction/variation and reduce image artifacts that otherwise occur due to variable frequency operation. An alternative embodiment dynamically controls an amount of light output from a backlight according to the variable frequency signal.

Abstract: A display device includes a display panel which includes gate lines and data lines, a gate driver electrically connected to the gate lines, a temperature sensor which includes at least three temperature sensing circuits which are disposed adjacent to the gate driver, and a voltage generating circuit which outputs a test voltage to each of the temperature sensing circuits and outputs a clock signal, which is compensated based on a result voltage having a lowest voltage level among result voltages provided from the temperature sensing circuits, to the gate driver.

Abstract: There is provided a display apparatus comprising: a backlight configured to output a first and a second light having a first and second color during a first and second field of a frame; a mapper configured to map an input image signal into a first and a second mapping data corresponding to the first and second light; a compensator configured to compensate a first and a second color mapping data on a basis of a first and a second DCC compensation data so as to generate a first and second color output image data; and a liquid crystal panel comprising a transmissive sub pixel configured to modulate the first and second light on a basis of the first and second color output data to display a first image having the first color and a second image having the second color.