Patents by Inventor Woon Shin

Woon Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110242140
    Abstract: In a method of driving a display panel, a gate signal is outputted to the display panel based on a first control signal. A gamma-corrected analog voltage is generated. A pre-charge compensating analog voltage is generated. A data voltage waveform is generated to include the generated gamma-corrected analog voltage and the generated pre-charge compensating analog voltage during one horizontal period of the display panel. The display panel has a pixel structure in which a data line is alternately connected to first and second subpixel columns adjacent to each other. The pre-charge compensating voltage has a level different from that of the gamma-corrected analog voltage where the latter represents a grayscale level represented by a received digital data signal. According to the method, display defects due to a difference of pre-charging levels used during plural horizontal periods may be decreased so that display quality of the display panel may be improved.
    Type: Application
    Filed: December 7, 2010
    Publication date: October 6, 2011
    Inventors: HYOUNG-RAE LEE, SEONG-IL KIM, SEUNG-WOON SHIN, JUNG-HOON KU, CHOONG-HWA KIM
  • Patent number: 7871897
    Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: January 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-woon Shin, Soo-jin Hong, Guk-hyon Yon, Si-young Choi, Sun-ghil Lee
  • Patent number: 7807543
    Abstract: A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: October 5, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-woon Shin, Tai-su Park, Si-young Choi, Soo-jin Hong, Mi-jin Kim
  • Publication number: 20100240207
    Abstract: Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 23, 2010
    Inventors: Young-Geun Park, Jae-Young Ahn, Jun-Kyu Yang, Dong-Woon Shin
  • Patent number: 7785985
    Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: August 31, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-woon Shin, Tai-su Park, Si-young Choi, Soo-jin Hong, Mi-jin Kim
  • Publication number: 20100210116
    Abstract: A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 19, 2010
    Inventors: Jae-Young AHN, Ki-Hyun Hwang, Young-Geun Park, Jun-Kyu Yang, Byong-Sun Ju, Dong-Woon Shin
  • Publication number: 20100162562
    Abstract: A method of manufacturing a rigid-flexible printed circuit board, including providing a base substrate in which coverlays are respectively formed on two sides of a flexible copper foil laminate on both sides of which inner circuit patterns are respectively formed; layering insulation layers and copper foil layers on portions of coverlays which are to be a rigid region of the flexible copper foil laminate; forming a via hole in the rigid region, and, simultaneously, forming first windows in the coverlays in a flexible region; forming outer circuit patterns including areas adjacent to the first windows; and applying solder resist in the rigid region to expose portions of the external circuit patterns, where the outer circuit patterns formed in the areas adjacent to the first windows include additional plating portions for covering portions of the coverlays.
    Type: Application
    Filed: March 8, 2010
    Publication date: July 1, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yang Je LEE, Il Woon Shin, Going Sik Kim, Doo Pyo Hong, Ha Il Kim, Dong Gi An
  • Publication number: 20100134401
    Abstract: A liquid crystal display (LCD) and a method of driving the LCD are provided. The LCD includes a display panel; and a timing controller providing a first data signal to the display panel during a first frame period, a second data signal to the display panel during a second frame period and a blank signal to the display panel during a blank period between the first and second frame periods, wherein the voltage of the blank signal varies among a plurality of levels between the voltage of the first data signal and the voltage of the second data signal.
    Type: Application
    Filed: May 19, 2009
    Publication date: June 3, 2010
    Inventors: Seung-Woon Shin, Young-Ki Kim, Sung-Woon Im, Jun-Ho Hwang
  • Publication number: 20100117141
    Abstract: In one aspect, a transistor comprises: a substrate body; a tunnel oxide layer on the body; a charge trapping layer on the tunnel oxide layer; a blocking layer on the charge trapping layer; a control gate on the blocking layer, the control gate having first and second sidewalls, the first and second sidewalls being spaced apart from each other by a first distance; and charge confinement features on the body, the charge confinement features being spaced apart from each other by a second distance that is greater than or substantially equal to the first distance, the charge confinement features suppressing or preventing migration of charge present in the charge trapping layer.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 13, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-woon Shin, Young-Kun Park, Jun-gyu Yang, Jae-young Ahn, Ki-hyun Hwang, Si-young Choi
  • Patent number: 7705247
    Abstract: A built-up printed circuit board includes stacked micro via-holes, each of which is provided for interconnection between layers in the printed circuit board, and in each of which a filling material, such as liquefied resin or conductive paste, is filled using a poly screen of a general screen printing machine.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: April 27, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Bong-Suck Kim, Gye-Soo Kim, Jong-Hyung Kim, Il-Woon Shin
  • Publication number: 20100082020
    Abstract: A medical laser apparatus having a capacitance sensor and a laser emission control device is provided, which can improve the safety by sensing whether a laser handpiece is in contact with a skin using the capacitance sensor and emitting a laser beam only when the handpiece is in contact with the skin, and which can improve the accuracy by making it possible to confirm whether the handpiece stands perpendicular to the skin surface.
    Type: Application
    Filed: September 19, 2007
    Publication date: April 1, 2010
    Inventors: Sung Huan GONG, Tae Ho HA, Jae Seon SEO, Sung Woon SHIN
  • Publication number: 20100055856
    Abstract: A method of forming an oxide layer on a trench, a method of forming a semiconductor device, and a semiconductor device, the method of forming an oxide layer on a trench including forming a first trench in a first portion of a substrate and a second trench in a second portion of the substrate, the first portion being different from the second portion, performing a plasma doping process on at least one of the first portion and the second portion to implant an impurity therein, and performing an oxidation process to form an oxide layer on the substrate, a thickness of the oxide layer being determined by the impurity implanted in the substrate.
    Type: Application
    Filed: August 27, 2009
    Publication date: March 4, 2010
    Inventors: Soo-Jin Hong, Jong-Ryeol Yoo, Dong-Woon Shin, Si-Young Choi, Sun-Ghil Lee
  • Publication number: 20090325356
    Abstract: Provided are methods of forming a low temperature deposition layer and methods of manufacturing a semiconductor device using the same. The method of manufacturing a semiconductor device comprises forming a mask layer exposing a gate pattern on a substrate on which the gate pattern is formed, forming a sacrifice layer on the mask layer and on a substrate not covered by the mask layer using a plasma ion immersion implantation and deposition (PIIID), and doping a substrate adjacent to both sidewalls of the gate pattern with an impurity.
    Type: Application
    Filed: April 29, 2009
    Publication date: December 31, 2009
    Inventors: Dong-Woon SHIN, Si-Young Choi, Tai-Su Park, Jong-Ryeol Yoo, Jong-Hoon Kang
  • Publication number: 20090311846
    Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.
    Type: Application
    Filed: May 14, 2009
    Publication date: December 17, 2009
    Inventors: Dong-Woon Shin, Soo-jin Hong, Guk-hyon Yon, Si-young Choi, Sun-ghil Lee
  • Patent number: 7604987
    Abstract: The invention relates to a bioreactor comprising a chamber for containing cells or tissue cultures within a culture medium. The bioreactor also comprises a detector capable of detecting a change in one or more metabolites associated with growth of the cell or tissue cultures within the chamber and a chamber drive capable of rotating the chamber at a first speed about a first axis and a second speed about a second axis, the second axis being disposed at an angle relative to the first axis. In use, the magnitude of the first speed and the second speed are independently variable of each other.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: October 20, 2009
    Assignee: National University of Singapore
    Inventors: Dietmar W. Hutmacher, Swee Hin Teoh, Manoja Ranawake, Woon Shin Chong, Keng Soon Ting, Kay Chiang Chua, Than Myint, Chum Mok Puah, Toon Tien Foo, Jan-Thorsten Schantz
  • Publication number: 20090203188
    Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
    Type: Application
    Filed: June 5, 2008
    Publication date: August 13, 2009
    Inventors: Dong-woon Shin, Tai-su Park, Si-young Choi, Soo-jin Hong, Mi-jin Kim
  • Publication number: 20090203189
    Abstract: A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
    Type: Application
    Filed: June 6, 2008
    Publication date: August 13, 2009
    Inventors: Dong-woon Shin, Tai-su Park, Si-Young Choi, Soo-Jin Hong, Mi-Jin Kim
  • Patent number: 7563872
    Abstract: The present invention relates to a protease, and more specifically to a protease derived from Aranicola proteolyticus, a gene coding for said enzyme, a gene expression system for said protease, a process for purifying the protease, and the uses of said protease in industrial applications, such as for example, detergents, cosmetics, leather processing agents, chemicals for laboratory research, solubilizing or softening agents for food, meat modifier, feed or food additives, or oil and fat separating agents, as well as pharmaceutical compositions.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: July 21, 2009
    Assignee: Korean Research Institute of Bioscience and Biotechnology
    Inventors: Ho-Yong Park, Kwang-Hee Son, Doo-Sang Park, Sang-Woon Shin, Hyun-Woo Oh, Mi-Gwang Kim, Dong-Ha Shin
  • Publication number: 20080282943
    Abstract: The present invention relates to a dust recycling and re-treating system and a method for the same, and in particular, to a dust recycling and re-treating system and a method for the same, which produces dusts generated from an incinerating and melting processing equipment for hazardous wastes, particularly, radioactive wastes, in a slurry form, and recycles and re-treats them within an existing melting furnace.
    Type: Application
    Filed: October 26, 2006
    Publication date: November 20, 2008
    Inventors: Jong Ho Bae, Young Hwan You, Choong Keun Kim, Jong Seo Choi, Sang Woon Shin, Tae Won Hwang, Seung Chul Daejeon, Seok Mo Choi
  • Publication number: 20080106198
    Abstract: A display apparatus includes a plasma display panel (PDP) and a filter having a panel side facing a display surface of the PDP and an opposing viewer side facing away from the display surface. The filter includes an external light shield having a first base unit and first pattern units. The first pattern units absorb external light from the viewer side and are substantially parallel to a first axis. The filter includes an electromagnetic interference (EMI) shield overlapping the external light shield. The EMI shield includes a second base unit and second pattern units. The second pattern units are conductive and substantially parallel to a second axis. An interior angle between the first axis and the second axis can be within a range of 40 to 50 degrees.
    Type: Application
    Filed: September 14, 2007
    Publication date: May 8, 2008
    Applicant: LG ELECTRONICS INC.
    Inventors: Hong CHA, Ji SOHN, Sam CHO, Woo JANG, Woon SHIN