Abstract: A gate driving module includes a gate driver and a gate signal generator. The gate driver generates a vertical start signal, a plurality of gate clock signals and a plurality of inverse gate clock signals based on a vertical start control signal, a plurality of gate clock control signals, a gate on voltage, a first gate off voltage and a second gate off voltage. The number of the gate clock signals is P. The number of the inverse gate clock signals is P. The number of the gate clock control signals is P. P is a positive integer equal to or greater than two. The gate signal generator generates a gate signal based on the vertical start signal, the gate clock signals and the inverse gate clock signals.

Abstract: A display apparatus including: gate lines extending in a first direction; data lines extending in a second direction intersecting the first direction; pixels connected to corresponding ones of the gate lines and data lines; a gate driver to drive the gate lines in response to a gate clock signal; a data driver to drive the data lines; a memory to store charge share signals corresponding to the gate lines; a timing controller controlling the data driver and the gate driver, in response to an externally input control signal and an image signal, and to output a gate pulse signal to the gate lines; and a clock generator configured to generate the gate clock signal in response to the gate pulse signal. The timing controller is configured to output the gate pulse signals according to the charge share signals.

Abstract: A display device includes a display panel, a timing controller, a data driver, a gate driver and a backlight unit. The gate driver sequentially outputs gate signals to gate lines. The backlight unit performs an on-operation during a high section of a backlight control signal and an off-operation during a low section of the backlight control signal. The gate signals includes first gate signals that are output during the high section of the backlight control signal and have a first pulse width and second gate signals that are output during the low section of the backlight control signal and have a second pulse width greater than the first pulse width.

Abstract: A method of driving a display panel includes receiving a screen selection signal which is configured to select one of a first screen of the display panel and a second screen of the display panel opposite to the first screen, selecting one of first option data, which are configured to display a normal image on the first screen, and second option data, which are configured to display the normal image on the second screen, based on the screen selection signal and driving the display panel based on the selected one of the first option data and the second option data.

Abstract: A method of driving a display panel, the method including outputting video data to a display panel during an N-th (N is a natural number) frame, outputting video data to the display panel during an (N+1)-th frame, comparing polarities of video data of the N-th frame and corresponding polarities of video data of the (N+1)-th frame, and controlling polarities of video data of an (N+2)-th frame, according to the result of the comparison.

Abstract: A display device includes gate lines, data lines, pixels, a gate driver, a data driver, and a timing controller. The gate lines extend in a first direction. The data lines extend in a second direction crossing the first direction. Each of the pixels is connected to a corresponding gate line of the gate lines and a corresponding data line of the data lines. The gate driver is configured to drive the gate lines. The data driver is configured to drive each data line of the data lines in response to a corresponding data signal. The timing controller is configured to, in response to an image signal and a control signal, apply the corresponding data signals to the data driver and control the gate driver. Each corresponding data signal reflects a kickback compensation value corresponding to a distance between the gate driver and the corresponding data line in the first direction.

Abstract: A control board in a display device includes terminals and a control circuit. The control circuit is configured to output a control signal an image signal through the terminals and to generate a drive voltage in response to a feedback signal, which is fed back to a second terminal of the terminals when a source voltage is applied to a first terminal of the terminals.

Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.

Abstract: A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3): HxSiAy(NR1R2)4-x-y??(1) HxSi(NAR3)4-x??(2) HxSi(R4)z(R5)4-x-z??(3) wherein, independently in the chemical formulas (1), (2), and (3), H is hydrogen, x is 0 to 3, Si is silicon, A is a halogen, y is 1 to 4, N is nitrogen, and R1, R2, R3, and R5 are each independently selected from the group of H, aryl, perhaloaryl, C1-8 alkyl, and C1-8 perhaloalkyl, and R4 is aryl in which at least one hydrogen is replaced with a halogen or C1-8 alkyl in which at least one hydrogen is replaced with a halogen

Abstract: A gate driving module includes a gate driver and a gate signal generator. The gate driver generates a vertical start signal, a plurality of gate clock signals and a plurality of inverse gate clock signals based on a vertical start control signal, a plurality of gate clock control signals, a gate on voltage, a first gate off voltage and a second gate off voltage. The number of the gate clock signals is P. The number of the inverse gate clock signals is P. The number of the gate clock control signals is P. P is a positive integer equal to or greater than two. The gate signal generator generates a gate signal based on the vertical start signal, the gate clock signals and the inverse gate clock signals.

Abstract: The torque assist system of the present invention includes a torque assist shaft having a first terminating part connected to the input shaft, an outer shaft and an inner shaft rotating independently from the outer shaft; a planetary gear set mounted on the inner shaft exposed to a second terminating part of the torque assist shaft; a clutch being disposed adjacent to the planetary gear set and operated by an external force; and an input gear mounted on the exposed inner shaft of the torque assist shaft and connected to the planetary gear set by the clutch to transmit power to an output gear mounted on the output shaft of the vehicle transmission.

Abstract: A method of manufacturing a rigid-flexible printed circuit board includes providing a base substrate in which coverlays are respectively formed on two sides of a flexible copper foil laminate on both sides of which inner circuit patterns and a first window are respectively formed; layering insulation layers and copper foil layers on portions of coverlays which are to be a rigid region of the base substrate; forming a via hole in the rigid region, and, simultaneously, forming a via hole to correspond to the first window in a flexible region; forming outer circuit patterns including areas adjacent to the first window; and applying solder resists in the rigid region to expose portions of external circuit patterns. The region adjacent to the via holes in the flexible region includes additional plating portions for covering the coverlays.

Abstract: A display device includes a display panel, a timing controller, a data driver, a gate driver and a backlight unit. The gate driver sequentially outputs gate signals to gate lines. The backlight unit performs an on-operation during a high section of a backlight control signal and an off-operation during a low section of the backlight control signal. The gate signals includes first gate signals that are output during the high section of the backlight control signal and have a first pulse width and second gate signals that are output during the low section of the backlight control signal and have a second pulse width greater than the first pulse width.

Abstract: A driving circuit including a timing control part, a driving voltage generating part, a voltage modifying part, and a slope control part. The voltage modifying part is configured to modify the gate-on voltage to a swing-on signal based on the kickback control signal, the swing-on signal including a slicing part, the slicing part including a falling portion during which a level of the swing-on signal falls from the first high level to a second high level lower than the first high level, and a rising portion during which the level of the swing-on signal rises from the second high level to the first high level. The slope control part is configured to decrease a slew rate of the rising portion in the swing-on signal and to output the swing-on signal decreased the slew rate of the rising portion as a gate-on signal.

Abstract: A method of manufacturing a rigid-flexible printed circuit board, including providing a base substrate in which coverlays are respectively formed on two sides of a flexible copper foil laminate on both sides of which inner circuit patterns are respectively formed; layering insulation layers and copper foil layers on portions of coverlays which are to be a rigid region of the flexible copper foil laminate; forming a via hole in the rigid region, and, simultaneously, forming first windows in the coverlays in a flexible region; forming outer circuit patterns including areas adjacent to the first windows; and applying solder resist in the rigid region to expose portions of the external circuit patterns, where the outer circuit patterns formed in the areas adjacent to the first windows include additional plating portions for covering portions of the coverlays.

Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.

Abstract: In a method of driving a display panel, a gate signal is outputted to the display panel based on a first control signal. A gamma-corrected analog voltage is generated. A pre-charge compensating analog voltage is generated. A data voltage waveform is generated to include the generated gamma-corrected analog voltage and the generated pre-charge compensating analog voltage during one horizontal period of the display panel. The display panel has a pixel structure in which a data line is alternately connected to first and second subpixel columns adjacent to each other. The pre-charge compensating voltage has a level different from that of the gamma-corrected analog voltage where the latter represents a grayscale level represented by a received digital data signal. According to the method, display defects due to a difference of pre-charging levels used during plural horizontal periods may be decreased so that display quality of the display panel may be improved.

Abstract: A display apparatus includes pixels connected to gate lines and data lines crossing the gate lines, a data driver which drives the data lines, a gate driver which drives the gate lines, a timing controller which controls the data driver and the gate driver in response to an image signal and a control signal and outputs a first kickback signal and a second kickback signal, and a voltage generator which outputs a first gate-on voltage and a second gate-on voltage in response to the first and second kickback signals to drive the gate lines. The gate driver drives a first group of gate lines in response to the first gate-on voltage and drives a second group of the gate lines in response to the second gate-on voltage.

Abstract: A display device includes first, second, and third gate lines. The display device further includes a first data line and a second data line neighboring the first data line. The display device further includes first, second, and third pixel electrodes connected to the first, second, and third gate lines, respectively, and further includes a fourth pixel electrode connected to the second gate line. The fourth pixel electrode is disposed between the first and third electrodes and neighbors each of the first, second, and third pixel electrodes. The first, second, and third pixel electrodes are connected to the first data line. The display device further comprises a gate driver for applying copies of a gate-on voltage to the gate lines, the gate-on voltage including a first voltage in a first horizontal period, a second voltage in a second horizontal period, and a third voltage in a third horizontal period.

Abstract: Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.