Abstract: An SSD device comprises a first port linking up with a first host using a first link, a second port linking up with the first host or a second host using a second link, and a port mode controller controlling the first port and the second port to change an operating mode from a dual port mode, in which the first port and the second port operate independently of each other, to a single port mode, in which only the first port operates. The port mode controller controls the second port to reset the second link in a state where the first link is linked up.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a transaction layer generating a transaction packet for transmission of a transaction, a data link layer generating a link packet including a protection code and a sequence number for the transaction packet and a link packet including a sequence number on the basis of the transaction packet, a physical layer generating a physical packet on the basis of the link packet and sequentially outputting the physical packet, a link training module performing negotiation for a link coupled through the physical layer and maintaining data information based on whether a link down occurring when the negotiation for the link is not performed is requested by a host or not, and a PCIe register storing information about the transaction layer, the data link layer, the physical layer, and the link training module.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: The present invention relates to a method for the synthesis of 2,5-furandicarboxylic acid, and more specifically, the present invention relates to a more efficient and economical method capable of preparing 2,5-furandicarboxylic acid having various functions with high purity and high yield, even without using a transition metal catalyst.

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

Abstract: A peripheral component interconnect express (PCIe) interface device is provided to include: a root complex configured to support a PCIe port, a memory connected to an input/output structure through the root complex, a switch connected to the root complex through a link and configured to transmit a transaction, and an end point connected to the switch through the link to transmit and receive a packet. The PCIe interface device may perform a link power management by changing a state of the link in response to a detection of an idle state of the link.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.

Abstract: An organoelectroluminescent device according to the present invention employs compounds of characteristic structures as a hole transport material and a dopant material in a hole injection layer or a hole transport layer, and in an emissive layer, respectively, and thus can be driven at a low voltage and realize highly efficient emission characteristics with excellent external quantum efficiency. Thus, the organoelectroluminescent device may be industrially advantageously used in a flexible display device, a flexible display device, a single-color or white-color flat lighting device, a single-color or shite-color flexible lighting device, and the like.

Abstract: Disclosed is an organic light-emitting device with high efficiency and long lifespan that uses an anthracene derivative having a characteristic structure as a host compound in a light-emitting layer of the organic light-emitting device and uses a compound having a characteristic structure as a compound for a hole transport layer.

Abstract: Disclosed is a highly efficient organic light-emitting device that uses an anthracene derivative having a characteristic structure as a host compound in a light-emitting layer of the organic light-emitting device and includes a capping layer formed using a compound having a characteristic structure in the organic light-emitting device.

Abstract: Disclosed is an organic light-emitting device with high efficiency and long lifespan that uses an anthracene derivative having a characteristic structure as a host compound in a light-emitting layer of the organic light-emitting device and uses a compound having a characteristic structure as a compound for an electron transport layer.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.

Abstract: Compounds, compositions, and methods for treating and/or preventing at least one disease, disorder, and/or condition N associated with E-selectin, galectin-3, and/or CXCR4 chemokine receptor activity are disclosed herein. For example, multimeric glycomimetic inhibitors of E-selectins, galectin-3, and/or CXCR4 chemokine receptors and their use for treating and/or preventing inflammatory diseases, fibrosis, and cancers are disclosed. Formula (I).

Abstract: Compounds, compositions, and methods for treatment and/or prevention of at least one disease, disorder, and/or condition by inhibiting binding of an E-selectin, galectin-3, or E-selectin and galectin-3 to ligands a disclosed. For example, heterobifunctional inhibitors of E-selectin and galectin-3 are described and pharmaceutical compositions comprising at least one such agent is described.

Abstract: A peripheral component interconnect express (PCIe) interface device is provided to include: a root complex configured to support a PCIe port, a memory connected to an input/output structure through the root complex, a switch connected to the root complex through a link and configured to transmit a transaction, and an end point connected to the switch through the link to transmit and receive a packet. The PCIe interface device may perform a link power management by changing a state of the link in response to a detection of an idle state of the link.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a transaction layer generating a transaction packet for transmission of a transaction, a data link layer generating a protection code for the transaction packet and a link packet including a sequence number on the basis of the transaction packet, a physical layer generating a physical packet on the basis of the link packet and sequentially outputting the physical packet, a link training module performing negotiation for a link coupled through the physical layer and maintaining data information based on whether a link down occurring when the negotiation for the link is not performed is requested by a host or not, and a PCIe register storing information about the transaction layer, the data link layer, the physical layer, and the link training module.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

Abstract: The present technology relates to an electronic device. A computing system may include a host and a peripheral component interconnect express (PCIe) device connected the host through a link. The host comprises a host memory and a storage device driver. The host memory may store information on a first target command to be executed in the PCIe device. The storage device driver may provide the first target command to the host memory and a notification message indicating that the first target command is stored in the host memory to the PCIe device. The PCIe device may request the host memory to register an address of the host memory in which a second target command to be executed in the PCIe device is stored through a preset protocol.