Patents by Inventor Wu Hsu
Wu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11796591Abstract: An apparatus comprising a battery and a circuit. The battery may be configured to provide a persistent power source. The circuit may comprise a processor, self-test logic, internal storage and logic circuitry. The self-test logic may be configured to perform a status check to determine an operating status of the logic circuitry. The processor may be configured to enable a first portion of the status check to be performed during a shutdown of the apparatus and a second portion of the status check to be performed during a bootup of the apparatus. The battery may provide the persistent power source to the internal storage after the shutdown of the apparatus. Parameters generated during the first portion may be stored in the internal storage. The parameters stored in the internal storage may be used with the second portion to determine the operating status of the logic circuitry.Type: GrantFiled: April 4, 2022Date of Patent: October 24, 2023Assignee: Ambarella International LPInventors: Praveen Jaini, Hsin-Wu Hsu, Hejia Yan
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Patent number: 11270183Abstract: An electronic module preparation layer (A) and a manufacturing method therefor. The electronic module preparation layer (A) comprises a substrate (10), multiple electronic modules (20) and two release layers (30, 40). The multiple electronic modules (20) are coated in the substrate (10) by means of the two release layers (30, 40) so as to provide a protective effect. When a user needs to input a program code to various electronic modules (20), since one of the release layers, i.e.Type: GrantFiled: December 29, 2017Date of Patent: March 8, 2022Inventor: Wu-Hsu Lin
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Publication number: 20210210362Abstract: An electronic module preparation layer (A) and a manufacturing method therefor. The electronic module preparation layer (A) comprises a substrate (10), multiple electronic modules (20) and two release layers (30, 40). The multiple electronic modules (20) are coated in the substrate (10) by means of the two release layers (30, 40) so as to provide a protective effect. When a user needs to input a program code to various electronic modules (20), since one of the release layers, i.e.Type: ApplicationFiled: December 29, 2017Publication date: July 8, 2021Inventor: Wu-Hsu Lin
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Patent number: 11006750Abstract: A shelf frame for a rack of shelves includes an elongated body; a ledge extending perpendicularly from a bottom edge of the elongated body, the ledge having a width equal to a height of the elongated body; an elongated enhancement disposed along a top edge of the elongated body, the enhancement being bent toward the ledge; two upright extensions disposed at two ends of the elongated body respectively; and a plurality of fasteners disposed in each of the two upright extensions. The two upright extensions and the elongated body are on the same plane. Each of the two upright extensions has a length equal to twice of the height of the elongated body.Type: GrantFiled: March 25, 2020Date of Patent: May 18, 2021Inventor: Wu Hsu Chiu
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Patent number: 10866281Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.Type: GrantFiled: April 19, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Pin Changchien, Hong-Chen Cheng, Pei-Ying Lin, Hsin-Wu Hsu
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Publication number: 20200329867Abstract: A shelf frame for a rack of shelves includes an elongated body; a ledge sticking inward from the elongated body and being perpendicular to the elongated body, the ledge having a width equal to that of the elongated body; an elongated enhancement disposed along an edge of the elongated body and being distal from the ledge, the enhancement being bent toward the ledge; two upright extensions disposed at two ends of the elongated body respectively; and a plurality of fasteners disposed at the extensions opposite to the ledge. The extensions and the elongated body are on the same plane and are parallel to each other. The extension has a length equal to twice of the width of the elongated body.Type: ApplicationFiled: March 25, 2020Publication date: October 22, 2020Inventor: WU HSU CHIU
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Patent number: 10626905Abstract: A shelving assembly includes at least one first post having an L-shaped section and including first apertures, two connection members at first ends respectively, and a retainer disposed on an outer surface of each connection member and including a neck and an enlarged head. A second post has an L-shaped section and includes second apertures and two T-shaped aperture members at second ends respectively. A size of the aperture member is greater than a diameter of the head. A length of the aperture member is at least 1.5 times of a diameter of the head. A width of a vertical part of the aperture member is greater than a diameter of the neck and smaller than the diameter of the head. The retainer passes through the aperture member to lock the neck in the vertical part, thereby joining the first and second posts.Type: GrantFiled: March 29, 2019Date of Patent: April 21, 2020Inventor: Wu Hsu Chiu
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Publication number: 20190242943Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.Type: ApplicationFiled: April 19, 2019Publication date: August 8, 2019Inventors: WEI-PIN CHANGCHIEN, HONG-CHEN CHENG, PEI-YING LIN, HSIN-WU HSU
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Patent number: 10267853Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.Type: GrantFiled: April 25, 2016Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Pin Changchien, Hong-Chen Cheng, Pei-Ying Lin, Hsin-Wu Hsu
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Patent number: 10037453Abstract: A capacitive fingerprint sensing module includes a flexible printed circuit board, a lower conductive adhesive layer, an upper conductive adhesive layer, and a positioning frame. The flexible printed circuit board has an upper surface and a lower surface. The upper surface has a finger pressing region and a first sensing layer. The lower surface has a second sensing layer. The lower conductive adhesive layer is formed on the second sensing layer and provided to cover second sensing electrodes mounted on the second sensing layer. The upper conductive adhesive layer is formed on the finger pressing region. The positioning frame has an opening facing upward and a slot. The flexible printed circuit board is inserted through the slot and embedded in the positioning frame. Accordingly, effects of conductivity enhancement and accuracy improvement of the capacitive fingerprint sensing module are produced.Type: GrantFiled: August 26, 2016Date of Patent: July 31, 2018Inventor: Wu-Hsu Lin
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Publication number: 20180060633Abstract: A capacitive fingerprint sensing module includes a flexible printed circuit board, a lower conductive adhesive layer, an upper conductive adhesive layer, and a positioning frame. The flexible printed circuit board has an upper surface and a lower surface. The upper surface has a finger pressing region and a first sensing layer. The lower surface has a second sensing layer. The lower conductive adhesive layer is formed on the second sensing layer and provided to cover second sensing electrodes mounted on the second sensing layer. The upper conductive adhesive layer is formed on the finger pressing region. The positioning frame has an opening facing upward and a slot. The flexible printed circuit board is inserted through the slot and embedded in the positioning frame. Accordingly, effects of conductivity enhancement and accuracy improvement of the capacitive fingerprint sensing module are produced.Type: ApplicationFiled: August 26, 2016Publication date: March 1, 2018Inventor: Wu-Hsu Lin
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Publication number: 20170330705Abstract: A switch assembly has a switch unit and a separating cap. The switch unit has a pressing element. The separating cap is attached to the switch unit and encloses the pressing element. Accordingly, glue filled into an object in which the switch assembly is mounted can be kept from attaching to the pressing element and the operation accuracy of the switch unit can be improved.Type: ApplicationFiled: May 12, 2016Publication date: November 16, 2017Inventor: Wu-Hsu LIN
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Publication number: 20170325017Abstract: An electrical speaker assembly has a speaker element and two caps. The speaker element has two sides. The caps are attached respectively to the two sides of the speaker element, and each cap has a resonance space between the cap and a corresponding one of the sides of the speaker element, wherein one of the caps has a wire notch defined in the cap.Type: ApplicationFiled: May 4, 2016Publication date: November 9, 2017Inventor: WU-HSU LIN
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Patent number: 9813803Abstract: An electrical speaker assembly has a speaker element and two caps. The speaker element has two sides. The caps are attached respectively to the two sides of the speaker element, and each cap has a resonance space between the cap and a corresponding one of the sides of the speaker element, wherein one of the caps has a wire notch defined in the cap.Type: GrantFiled: May 4, 2016Date of Patent: November 7, 2017Inventor: Wu-Hsu Lin
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Patent number: 9760775Abstract: A retina identifying module has a retina identifying chip and an encapsulation body. The encapsulation body is transparent, is mounted on and enclosing the retina identifying chip, and has a convex top face. Accordingly, the thickness of the retina identifying module can be effectively reduced.Type: GrantFiled: May 26, 2016Date of Patent: September 12, 2017Inventor: Wu-Hsu Lin
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Patent number: 9760773Abstract: A smart card has a bottom layer, a circuit board, a microprocessor, a retina identifying module, an operation unit, and a top layer. The microprocessor is mounted on the circuit board. The operation unit is mounted on the circuit board and is electrically connected with the microprocessor. The retina identifying module is mounted on the circuit board, is electrically connected with the microprocessor, and has a retina identifying chip and an encapsulation. The retina identifying chip is mounted on the circuit board and is electrically connected with the microprocessor. The encapsulation body is transparent, is mounted on and encloses the retina identifying chip, and has a convex top face. The top layer is mounted on the circuit board to cover the microprocessor, the operation unit and the retina identifying module.Type: GrantFiled: June 1, 2016Date of Patent: September 12, 2017Inventor: Wu-Hsu Lin
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Patent number: 9754976Abstract: An element substrate is provided, including a substrate, a metal layer, a planarization layer and a first conductive layer. The metal layer is disposed on the substrate. The planarization layer is located on the metal layer, wherein the planarization layer includes a contact hole, the contact hole has a continuous wall and a bottom, the bottom exposes the metal layer, and the bottom of the contact hole has a first width. The first conductive layer is located on the planarization layer, wherein the first conductive layer includes an opening, the opening exposes the contact hole, and the opening has a second width above the contact hole, wherein the relationship of the first width and the second width is modified to decrease illumination loss and to prevent problems of shot-circuiting and insufficient capacitance.Type: GrantFiled: November 4, 2014Date of Patent: September 5, 2017Assignee: INNOLUX CORPORATIONInventors: Yueh-Ting Chung, Shao-Wu Hsu, Yung-Hsin Lu, Jyun-Yu Chen, Kuan-Yu Chiu, Chao-Hsiang Wang
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Publication number: 20170176525Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.Type: ApplicationFiled: April 25, 2016Publication date: June 22, 2017Inventors: WEI-PIN CHANGCHIEN, HONG-CHEN CHENG, PEI-YING LIN, HSIN-WU HSU
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Patent number: 9342774Abstract: The smart card has a supporting body, a flexible circuit board, a holding frame, a fingerprint identifying module, and a cover sheet. The flexible circuit board is attached to the top of the supporting body and has a data chip. The holding frame is mounted on the flexible circuit board and has a holding recess and an opening. The fingerprint identifying module is mounted in the holding frame and has an identifying chip, a flexible electrical connection sheet, and a hard supporting board to provide a supporting effect to the identifying chip. The cover sheet is attached to the top of the flexible circuit board and has an identifying window. The identifying window is defined through the cover sheet and corresponds to the identifying chip in position to allow the identifying chip to be exposed from the identifying window.Type: GrantFiled: July 8, 2015Date of Patent: May 17, 2016Inventor: Wu-Hsu Lin
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Publication number: 20160079279Abstract: An element substrate is provided, including a substrate, a metal layer, a planarization layer and a first conductive layer. The metal layer is disposed on the substrate. The planarization layer is located on the metal layer, wherein the planarization layer includes a contact hole, the contact hole has a continuous wall and a bottom, the bottom exposes the metal layer, and the bottom of the contact hole has a first width. The first conductive layer is located on the planarization layer, wherein the first conductive layer includes an opening, the opening exposes the contact hole, and the opening has a second width above the contact hole, wherein the relationship of the first width and the second width is modified to decrease illumination loss and to prevent problems of shot-circuiting and insufficient capacitance.Type: ApplicationFiled: November 4, 2014Publication date: March 17, 2016Inventors: Yueh-Ting CHUNG, Shao-Wu HSU, Yung-Hsin LU, Jyun-Yu CHEN, Kuan-Yu CHIU, Chao-Hsiang WANG