Patents by Inventor Wu Hsu

Wu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11796591
    Abstract: An apparatus comprising a battery and a circuit. The battery may be configured to provide a persistent power source. The circuit may comprise a processor, self-test logic, internal storage and logic circuitry. The self-test logic may be configured to perform a status check to determine an operating status of the logic circuitry. The processor may be configured to enable a first portion of the status check to be performed during a shutdown of the apparatus and a second portion of the status check to be performed during a bootup of the apparatus. The battery may provide the persistent power source to the internal storage after the shutdown of the apparatus. Parameters generated during the first portion may be stored in the internal storage. The parameters stored in the internal storage may be used with the second portion to determine the operating status of the logic circuitry.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: October 24, 2023
    Assignee: Ambarella International LP
    Inventors: Praveen Jaini, Hsin-Wu Hsu, Hejia Yan
  • Patent number: 11270183
    Abstract: An electronic module preparation layer (A) and a manufacturing method therefor. The electronic module preparation layer (A) comprises a substrate (10), multiple electronic modules (20) and two release layers (30, 40). The multiple electronic modules (20) are coated in the substrate (10) by means of the two release layers (30, 40) so as to provide a protective effect. When a user needs to input a program code to various electronic modules (20), since one of the release layers, i.e.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 8, 2022
    Inventor: Wu-Hsu Lin
  • Publication number: 20210210362
    Abstract: An electronic module preparation layer (A) and a manufacturing method therefor. The electronic module preparation layer (A) comprises a substrate (10), multiple electronic modules (20) and two release layers (30, 40). The multiple electronic modules (20) are coated in the substrate (10) by means of the two release layers (30, 40) so as to provide a protective effect. When a user needs to input a program code to various electronic modules (20), since one of the release layers, i.e.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 8, 2021
    Inventor: Wu-Hsu Lin
  • Patent number: 11006750
    Abstract: A shelf frame for a rack of shelves includes an elongated body; a ledge extending perpendicularly from a bottom edge of the elongated body, the ledge having a width equal to a height of the elongated body; an elongated enhancement disposed along a top edge of the elongated body, the enhancement being bent toward the ledge; two upright extensions disposed at two ends of the elongated body respectively; and a plurality of fasteners disposed in each of the two upright extensions. The two upright extensions and the elongated body are on the same plane. Each of the two upright extensions has a length equal to twice of the height of the elongated body.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: May 18, 2021
    Inventor: Wu Hsu Chiu
  • Patent number: 10866281
    Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Pin Changchien, Hong-Chen Cheng, Pei-Ying Lin, Hsin-Wu Hsu
  • Publication number: 20200329867
    Abstract: A shelf frame for a rack of shelves includes an elongated body; a ledge sticking inward from the elongated body and being perpendicular to the elongated body, the ledge having a width equal to that of the elongated body; an elongated enhancement disposed along an edge of the elongated body and being distal from the ledge, the enhancement being bent toward the ledge; two upright extensions disposed at two ends of the elongated body respectively; and a plurality of fasteners disposed at the extensions opposite to the ledge. The extensions and the elongated body are on the same plane and are parallel to each other. The extension has a length equal to twice of the width of the elongated body.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 22, 2020
    Inventor: WU HSU CHIU
  • Patent number: 10626905
    Abstract: A shelving assembly includes at least one first post having an L-shaped section and including first apertures, two connection members at first ends respectively, and a retainer disposed on an outer surface of each connection member and including a neck and an enlarged head. A second post has an L-shaped section and includes second apertures and two T-shaped aperture members at second ends respectively. A size of the aperture member is greater than a diameter of the head. A length of the aperture member is at least 1.5 times of a diameter of the head. A width of a vertical part of the aperture member is greater than a diameter of the neck and smaller than the diameter of the head. The retainer passes through the aperture member to lock the neck in the vertical part, thereby joining the first and second posts.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 21, 2020
    Inventor: Wu Hsu Chiu
  • Publication number: 20190242943
    Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Inventors: WEI-PIN CHANGCHIEN, HONG-CHEN CHENG, PEI-YING LIN, HSIN-WU HSU
  • Patent number: 10267853
    Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Pin Changchien, Hong-Chen Cheng, Pei-Ying Lin, Hsin-Wu Hsu
  • Patent number: 10037453
    Abstract: A capacitive fingerprint sensing module includes a flexible printed circuit board, a lower conductive adhesive layer, an upper conductive adhesive layer, and a positioning frame. The flexible printed circuit board has an upper surface and a lower surface. The upper surface has a finger pressing region and a first sensing layer. The lower surface has a second sensing layer. The lower conductive adhesive layer is formed on the second sensing layer and provided to cover second sensing electrodes mounted on the second sensing layer. The upper conductive adhesive layer is formed on the finger pressing region. The positioning frame has an opening facing upward and a slot. The flexible printed circuit board is inserted through the slot and embedded in the positioning frame. Accordingly, effects of conductivity enhancement and accuracy improvement of the capacitive fingerprint sensing module are produced.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: July 31, 2018
    Inventor: Wu-Hsu Lin
  • Publication number: 20180060633
    Abstract: A capacitive fingerprint sensing module includes a flexible printed circuit board, a lower conductive adhesive layer, an upper conductive adhesive layer, and a positioning frame. The flexible printed circuit board has an upper surface and a lower surface. The upper surface has a finger pressing region and a first sensing layer. The lower surface has a second sensing layer. The lower conductive adhesive layer is formed on the second sensing layer and provided to cover second sensing electrodes mounted on the second sensing layer. The upper conductive adhesive layer is formed on the finger pressing region. The positioning frame has an opening facing upward and a slot. The flexible printed circuit board is inserted through the slot and embedded in the positioning frame. Accordingly, effects of conductivity enhancement and accuracy improvement of the capacitive fingerprint sensing module are produced.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 1, 2018
    Inventor: Wu-Hsu Lin
  • Publication number: 20170330705
    Abstract: A switch assembly has a switch unit and a separating cap. The switch unit has a pressing element. The separating cap is attached to the switch unit and encloses the pressing element. Accordingly, glue filled into an object in which the switch assembly is mounted can be kept from attaching to the pressing element and the operation accuracy of the switch unit can be improved.
    Type: Application
    Filed: May 12, 2016
    Publication date: November 16, 2017
    Inventor: Wu-Hsu LIN
  • Publication number: 20170325017
    Abstract: An electrical speaker assembly has a speaker element and two caps. The speaker element has two sides. The caps are attached respectively to the two sides of the speaker element, and each cap has a resonance space between the cap and a corresponding one of the sides of the speaker element, wherein one of the caps has a wire notch defined in the cap.
    Type: Application
    Filed: May 4, 2016
    Publication date: November 9, 2017
    Inventor: WU-HSU LIN
  • Patent number: 9813803
    Abstract: An electrical speaker assembly has a speaker element and two caps. The speaker element has two sides. The caps are attached respectively to the two sides of the speaker element, and each cap has a resonance space between the cap and a corresponding one of the sides of the speaker element, wherein one of the caps has a wire notch defined in the cap.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 7, 2017
    Inventor: Wu-Hsu Lin
  • Patent number: 9760775
    Abstract: A retina identifying module has a retina identifying chip and an encapsulation body. The encapsulation body is transparent, is mounted on and enclosing the retina identifying chip, and has a convex top face. Accordingly, the thickness of the retina identifying module can be effectively reduced.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 12, 2017
    Inventor: Wu-Hsu Lin
  • Patent number: 9760773
    Abstract: A smart card has a bottom layer, a circuit board, a microprocessor, a retina identifying module, an operation unit, and a top layer. The microprocessor is mounted on the circuit board. The operation unit is mounted on the circuit board and is electrically connected with the microprocessor. The retina identifying module is mounted on the circuit board, is electrically connected with the microprocessor, and has a retina identifying chip and an encapsulation. The retina identifying chip is mounted on the circuit board and is electrically connected with the microprocessor. The encapsulation body is transparent, is mounted on and encloses the retina identifying chip, and has a convex top face. The top layer is mounted on the circuit board to cover the microprocessor, the operation unit and the retina identifying module.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 12, 2017
    Inventor: Wu-Hsu Lin
  • Patent number: 9754976
    Abstract: An element substrate is provided, including a substrate, a metal layer, a planarization layer and a first conductive layer. The metal layer is disposed on the substrate. The planarization layer is located on the metal layer, wherein the planarization layer includes a contact hole, the contact hole has a continuous wall and a bottom, the bottom exposes the metal layer, and the bottom of the contact hole has a first width. The first conductive layer is located on the planarization layer, wherein the first conductive layer includes an opening, the opening exposes the contact hole, and the opening has a second width above the contact hole, wherein the relationship of the first width and the second width is modified to decrease illumination loss and to prevent problems of shot-circuiting and insufficient capacitance.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: September 5, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Yueh-Ting Chung, Shao-Wu Hsu, Yung-Hsin Lu, Jyun-Yu Chen, Kuan-Yu Chiu, Chao-Hsiang Wang
  • Publication number: 20170176525
    Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.
    Type: Application
    Filed: April 25, 2016
    Publication date: June 22, 2017
    Inventors: WEI-PIN CHANGCHIEN, HONG-CHEN CHENG, PEI-YING LIN, HSIN-WU HSU
  • Patent number: 9342774
    Abstract: The smart card has a supporting body, a flexible circuit board, a holding frame, a fingerprint identifying module, and a cover sheet. The flexible circuit board is attached to the top of the supporting body and has a data chip. The holding frame is mounted on the flexible circuit board and has a holding recess and an opening. The fingerprint identifying module is mounted in the holding frame and has an identifying chip, a flexible electrical connection sheet, and a hard supporting board to provide a supporting effect to the identifying chip. The cover sheet is attached to the top of the flexible circuit board and has an identifying window. The identifying window is defined through the cover sheet and corresponds to the identifying chip in position to allow the identifying chip to be exposed from the identifying window.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 17, 2016
    Inventor: Wu-Hsu Lin
  • Publication number: 20160079279
    Abstract: An element substrate is provided, including a substrate, a metal layer, a planarization layer and a first conductive layer. The metal layer is disposed on the substrate. The planarization layer is located on the metal layer, wherein the planarization layer includes a contact hole, the contact hole has a continuous wall and a bottom, the bottom exposes the metal layer, and the bottom of the contact hole has a first width. The first conductive layer is located on the planarization layer, wherein the first conductive layer includes an opening, the opening exposes the contact hole, and the opening has a second width above the contact hole, wherein the relationship of the first width and the second width is modified to decrease illumination loss and to prevent problems of shot-circuiting and insufficient capacitance.
    Type: Application
    Filed: November 4, 2014
    Publication date: March 17, 2016
    Inventors: Yueh-Ting CHUNG, Shao-Wu HSU, Yung-Hsin LU, Jyun-Yu CHEN, Kuan-Yu CHIU, Chao-Hsiang WANG