Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.

Abstract: Methods for encoding and decoding Polar codes are provided, together with apparatuses for performing the methods. An encoding method combines first and second sequences of information bits and CRC bits and a plurality of frozen bits into an input vector. The input vector is multiplied by a generator matrix for a Polar code to produce a concatenated codeword. A decoding method receives such a codeword and produces a decoded vector by generating successive levels of a decision tree. For a first number of levels of the decision tree, paths beyond a first maximum number of most probable paths are discarded. For a second number of levels of the decision tree, paths beyond a second maximum number of most probable paths are discarded. In some cases, the decoding method may have improved performance compared to some decoding methods for non-concatenated codewords.

Abstract: Methods, apparatuses, and systems for implementing error-correction in communication systems, particularly wireless communication systems, are provided. A Polar code-based encoding method combines first and second pluralities of information bits and error-correcting code bits, and a plurality of frozen bits, into an input vector. The input vector is encoded according to a Polar code to produce a first codeword, which improves the probability of successfully transmitting and receiving the codeword over a physical channel in the communication system.

Abstract: General polar codes are disclosed that encode symbols of a q-ary alphabet, where q?2. Systems and methods are also disclosed for performing code rate matching when using general polar codes. In one embodiment, a method performed at a transmitter includes receiving a plurality of bits at a polar encoder. The plurality of bits represent a plurality of q-ary symbols, where q>2. The method further includes encoding the plurality of bits using the polar encoder to generate a codeword of q-ary symbols represented by bits. The method further includes puncturing the codeword according to a puncturing pattern to obtain a punctured codeword having a reduced bit length.

Abstract: A transmitter and receiver are provided for communication over a noisy channel in a wireless communications system. The transmitter and receiver use polar coding to provide reliability of data transmission over the noisy wireless channel. In addition, signature bits are inserted in some unreliable bit positions of the polar code. For a given codeword, the receiver with knowledge of the signature can more effectively decode the codeword. Cyclic redundancy check (CRC) bits may also included in the input vector to assist in decoding.

Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.

Abstract: Coding sub-channel selection involves, in an embodiment, determining, from sub-channels that are defined by a code and that have associated reliabilities for input bits at input bit positions, a first number of the sub-channels to carry bits that are to be encoded. A second number of the sub-channels, greater than the first number, are selected. The second number of sub-channels are selected to provide exactly the first number sub-channels to be available to carry the bits that are to be encoded.

Abstract: An ordered number sequence may be determined based on an ordered sub-channel sequence specifying an order of N sub-channels that are defined by a code and that have associated reliabilities for input bits at N input bit positions. The ordered number sequence represents the ordered sub-channel sequence as a sequence of fewer than N numbers. The numbers in the ordered number sequence indicate the sub-channels, by representing numbers of the sub-channels for example, from different subsets of the N sub-channels, that appear in the order specified by the ordered sub-channel sequence. Using ordered number sequences, longer ordered sub-channel sequences could be constructed from smaller ordered sub-channel sequences, and/or sub-channels that to be selected from a longer ordered sub-channel sequence could be divided into two or more parts, with each part to be selected from shorter ordered sub-channel sequences.

Abstract: A number K of N sub-channels that are defined by a code and that have associated reliabilities for input bits at N input bit positions, are to be selected to carry bits that are to be encoded. A localization area that includes multiple sub-channels and is located below fewer than K of the N sub-channels in a partial order of the N sub-channels is determined based on one or more coding parameters. The fewer than K sub-channels of the N sub-channels above the localization area in the partial order are selected, and a number of sub-channels from those in the localization area are also selected. The selected fewer than K sub-channels and the number of sub-channels selected from those in the localization area together include K sub-channels to carry the bits that are to be encoded.

Abstract: An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

Abstract: Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.

Abstract: In reduced-stage polar decoding, a received word that is based on an N-bit codeword of a polar code is decoded using fewer than log2N Log Likelihood Ratio (LLR) stages. Decoding uses a reduced stage decoding configuration. In an embodiment, such a configuration includes at least one higher-order LLR stage with nodes implementing functions that are based on a combination of lower-order polar code kernels.

Abstract: Methods and systems for blind detection. At the encoder, a code word is encoded using a polar coder, where the input vector includes a user equipment (UE)-specific frozen sequence in the frozen bit positions. At the decoder, a set of short listed channel candidates is generated based on decoding using the UE-specific frozen sequence.

Abstract: Systems and methods are disclosed for performing rate matching when using general polar codes. In one embodiment, a method of generating a codeword includes receiving bits at a polar encoder and encoding the bits using polar encoder kernels. The polar encoder kernels include a first kernel and a second kernel. The first kernel receives a set of input q-ary symbols and modifies the set of input q-ary symbols according to a first kernel generator matrix to produce a set of output q-ary symbols. The second kernel receives a set of input l-ary symbols, where l does not equal q, and modifies the set of input l-ary symbols according to a second kernel generator matrix to produce a set of output l-ary symbols. For example, the first kernel may be a binary kernel and the second kernel may be a Reed-Solomon (RS) based kernel.

Abstract: A first error-detecting code (EDC) is computed based on a first segment of a block of information that is to be encoded, and a second EDC is computed based on at least a second segment of the block of information. The first EDC is masked with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC. The first masking segment and the second masking segment are associated with a target receiver of the block of information. A codeword is generated based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC. This type of coding could be useful to support early termination of blind detection at a decoder, for example.

Abstract: The present disclosure relates to multiple-symbol combination based decoding for general polar codes. Multiple-symbol combination based decoding of a received word that is based on a codeword involves determining whether all nodes at an intermediate stage of the multiple-symbol combination based decoding, which provide their outputs as inputs to a subset of nodes at a next stage of the multi-symbol combination based decoding, are associated with trust symbols in the received word that have a higher reliability of being successfully decoded than doubt symbols in the received word. A hard decision is performed in response to a positive determination.

Abstract: Systems and methods are disclosed that relate to performing rate matching when using polar codes. In one embodiment, a plurality of bits are received at a polar encoder. A value is obtained that corresponds to at least one of: a coding rate to be used to transmit the plurality of bits, and a number of coded bits to be used to transmit the plurality of bits. It is determined which range of values the value falls within, and an information sequence is obtained that corresponds to the range the value falls within. The plurality of bits are mapped to a subset of positions of an input vector according to the information sequence. The remaining positions of the input vector are set as frozen values that are known by a decoder. The input vector is then encoded in the polar encoder to generate a codeword.

Abstract: General polar codes are disclosed that encode symbols of a q-ary alphabet, where q?2. Systems and methods are also disclosed for performing code rate matching when using general polar codes. In one embodiment, a method performed at a transmitter includes receiving a plurality of bits at a polar encoder. The plurality of bits represent a plurality of q-ary symbols, where q>2. The method further includes encoding the plurality of bits using the polar encoder to generate a codeword of q-ary symbols represented by bits. The method further includes puncturing the codeword according to a puncturing pattern to obtain a punctured codeword having a reduced bit length.

Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.

Abstract: Systems and methods for Polar encoding with a blockwise checksum are provided. The method involves processing a set of K information blocks to produce a blockwise checksum with u blocks, where K>=2, and u>=1, and where each information block or checksum block contains P bits. The blockwise checksum may, for example, be a Fletcher checksum. The Polar code may be based on an m-fold Kronecker product matrix. Then, an N-bit input vector is produced with P×K information bits and the P×u blockwise checksum bits, and with N?PK?Pu frozen bits, where N=2m where m>=2. The N-bit input vector is processed to produce a result equivalent to multiplying the input vector by a Polar code generator matrix to produce a codeword. The codeword is then transmitted or stored.