Abstract: General polar codes are disclosed that encode symbols of a q-ary alphabet, where q?2. Systems and methods are also disclosed for performing code rate matching when using general polar codes. In one embodiment, a method performed at a transmitter includes receiving a plurality of bits at a polar encoder. The plurality of bits represent a plurality of q-ary symbols, where q>2. The method further includes encoding the plurality of bits using the polar encoder to generate a codeword of q-ary symbols represented by bits. The method further includes puncturing the codeword according to a puncturing pattern to obtain a punctured codeword having a reduced bit length.

Abstract: The present disclosure relates to multiple-symbol combination based decoding for general polar codes. Multiple-symbol combination based decoding of a received word that is based on a codeword involves determining whether all nodes at an intermediate stage of the multiple-symbol combination based decoding, which provide their outputs as inputs to a subset of nodes at a next stage of the multi-symbol combination based decoding, are associated with trust symbols in the received word that have a higher reliability of being successfully decoded than doubt symbols in the received word. A hard decision is performed in response to a positive determination.

Abstract: Systems and methods are disclosed that relate to performing rate matching when using polar codes. In one embodiment, a plurality of bits are received at a polar encoder. A value is obtained that corresponds to at least one of: a coding rate to be used to transmit the plurality of bits, and a number of coded bits to be used to transmit the plurality of bits. It is determined which range of values the value falls within, and an information sequence is obtained that corresponds to the range the value falls within. The plurality of bits are mapped to a subset of positions of an input vector according to the information sequence. The remaining positions of the input vector are set as frozen values that are known by a decoder. The input vector is then encoded in the polar encoder to generate a codeword.

Abstract: A first error-detecting code (EDC) is computed based on a first segment of a block of information that is to be encoded, and a second EDC is computed based on at least a second segment of the block of information. The first EDC is masked with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC. The first masking segment and the second masking segment are associated with a target receiver of the block of information. A codeword is generated based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC. This type of coding could be useful to support early termination of blind detection at a decoder, for example.

Abstract: Systems and methods are disclosed for performing rate matching when using general polar codes. In one embodiment, a method of generating a codeword includes receiving bits at a polar encoder and encoding the bits using polar encoder kernels. The polar encoder kernels include a first kernel and a second kernel. The first kernel receives a set of input q-ary symbols and modifies the set of input q-ary symbols according to a first kernel generator matrix to produce a set of output q-ary symbols. The second kernel receives a set of input l-ary symbols, where l does not equal q, and modifies the set of input l-ary symbols according to a second kernel generator matrix to produce a set of output l-ary symbols. For example, the first kernel may be a binary kernel and the second kernel may be a Reed-Solomon (RS) based kernel.

Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.

Abstract: Systems and methods for Polar encoding with a blockwise checksum are provided. The method involves processing a set of K information blocks to produce a blockwise checksum with u blocks, where K>=2, and u>=1, and where each information block or checksum block contains P bits. The blockwise checksum may, for example, be a Fletcher checksum. The Polar code may be based on an m-fold Kronecker product matrix. Then, an N-bit input vector is produced with P×K information bits and the P×u blockwise checksum bits, and with N?PK?Pu frozen bits, where N=2m where m>=2. The N-bit input vector is processed to produce a result equivalent to multiplying the input vector by a Polar code generator matrix to produce a codeword. The codeword is then transmitted or stored.

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

Abstract: Methods for encoding and decoding Polar codes are provided, together with apparatuses for performing the methods. An encoding method combines first and second sequences of information bits and CRC bits and a plurality of frozen bits into an input vector. The input vector is multiplied by a generator matrix for a Polar code to produce a concatenated codeword. A decoding method receives such a codeword and produces a decoded vector by generating successive levels of a decision tree. For a first number of levels of the decision tree, paths beyond a first maximum number of most probable paths are discarded. For a second number of levels of the decision tree, paths beyond a second maximum number of most probable paths are discarded. In some cases, the decoding method may have improved performance compared to some decoding methods for non-concatenated codewords.

Abstract: A signature-enabled Polar code encoder and decoder are provided. Signature bits are inserted in some unreliable bit positions. Different signature bits are inserted for different receivers. For a given codeword, only the receiver with knowledge of the signature can decode the codeword. Cyclic redundancy check (CRC) bits may be included in the input vector to assist in decoding.

Abstract: A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

Abstract: Methods and devices are disclosed for receiving and decoding sparsely encoded data sequences using a message passing algorithm (MPA) or maximum likelihood sequence estimation (MLSE). Such data sequences may be used in wireless communications systems supporting multiple access, such as sparse code multiple access (SCMA) systems. The Methods and devices reduce the number of states in a search space for each received signal and associated function node based on a search threshold based on a characteristic related to the received signal and/or to a quality of a resource element over which the received signal is transmitted.

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.

Abstract: A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.

Abstract: A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.

Abstract: Methods and apparatuses relating to QR decomposition using a multiple execution unit processing system are provided. A method includes receiving input values at the processing system and generating a first set of values based on the input values, where at least some of the first values are computed in parallel. A second set of values are generated recursively based on values in the first set. A third set of values are generated based on values in the second set, where at least some of the values in the third set are computed in parallel. The recursive component may be simplified to consist of one or more low latency operations. The processing performance of operations relating to QR decomposition may therefore be improved by using the parallelism available in multiple execution unit systems.

Abstract: An asynchronous multiple-core processor may be adapted for carrying out sets of known tasks, such as the tasks in the LAPACK and BLAS packages. Conveniently, the known tasks may be handled by the asynchronous multiple-core processor in a manner that may be considered to be more power efficient than carrying out the same known tasks on a single-core processor. Indeed, some of the power savings are realized through the use of token-based single core processors. Use of such token-based single core processors may be considered to be power efficient due to the lack of a global clock tree.

Abstract: A self-timed parallelized multi-core processor and method for operating the processor are provided. The processor has an instruction decoder unit to receive a program code instruction, determine an operating code and latency for the program code instructions, and assign a loop index to the program code instruction. The processor further includes an instruction decomposer unit coupled to the instruction decoder unit, the instruction decomposer configured to create a primitive by decomposing the instruction, replace the loop index with a core index, and broadcast the primitive. The processor further has a plurality of self-timed processing cores coupled to the instruction decomposer unit, each core having a unique core index and having a dispatch unit for comparing the core index in the primitive with the core index of its processing core, each core acting on the primitive when the index of the processing core is within a threshold of the core index.