Abstract: Disclosed are a polyethylene glycol conjugate drug, and a preparation method therefor and the use thereof. Specifically, the present invention relates to a polyethylene glycol conjugate drug represented by formula A or a pharmaceutically acceptable salt thereof, a method for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, an intermediate for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, and the use of the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof in the preparation of a drug.

Abstract: A method of forming an electrical connection between a buried power rail (BPR) of an unfinished complementary field effect transistor (CFET) and a source or drain epitaxial growth of a lower level of the CFET is provided. The method includes performing silicon epitaxial growth in a lower level of the CFET, adding a contact material to a portion of an exposed portion of the silicon epitaxial growth in the lower level, the exposed portion of the silicon epitaxial growth being located in a vertical slot of the unfinished CFET structure, adding a conductive material within a vertical channel, the conductive material being in contact with the added contact material and the BPR to form an electrical connection between the portion of the exposed portion of the silicon epitaxial growth and the BPR and etching back a portion of the added conductive material within the vertical channel.

Abstract: A screen mirroring display method includes a destination device receiving a first message from a first source device and a second message from a second source device, where the first message includes a first drawing instruction. The first drawing instruction instructs the destination device to draw a first target control in a first interface displayed by the first source device. The second message includes a second drawing instruction. The second drawing instruction instructs the destination device to draw a second target control in a second interface displayed by the second source device. Then the destination device draws a screen mirroring interface according to the first drawing instruction and the second drawing instruction, where the screen mirroring interface includes the first target control and the second target control.

Abstract: An object drag method includes a first terminal that displays an object on a display of the first terminal. The first terminal receives a drag operation from a user. The drag operation initiates a drag for the object. The first terminal displays, on the display of the first terminal in response to the drag operation, an animation in which the object moves with the drag operation. The first terminal sends drag data to a second terminal after determining that a drag intent of the user is a cross-device drag. The drag data enables the second terminal to display the object on a display of the second terminal.

Abstract: A screen mirroring display method implemented by a first electronic device, where the method includes displaying a first display interface, receiving a screen mirroring instruction for projecting the first display interface onto a second electronic device, determining a first target control in the first display interface in response to the screen mirroring instruction, and sending a first message to the second electronic device, where the first message includes a drawing instruction of the first target control to prompt the second electronic device to draw a first screen mirroring interface according to the drawing instruction, where the first screen mirroring interface includes the first target control.

Abstract: A terminal displays an application window of a first application on a display screen of the terminal. The application window includes a plurality of elements. After receiving a first operation, the terminal displays an animation in which the application window moves. When determining that the application window moves to a specified area of the display screen of the terminal, the terminal displays a live window on the display screen of the terminal. The live window includes some elements in the application window.

Abstract: This application provides a cross-device object drag method and a device, and relates to the field of electronic devices. This improves usage efficiency of collaborative use of a plurality of terminals, makes drag more direct and explicit, and improves user experience in drag. A specific solution is as follows: A first terminal displays an object on a display of the first terminal. The first terminal receives a drag operation input by a user. The drag operation is used to initiate drag for the object. The first terminal displays, on the display of the first terminal in response to the drag operation, an animation in which the object moves with the drag operation. The first terminal sends drag data to a second terminal after determining that a drag intent of the user is cross-device drag. The drag data is used by the second terminal to display the object on a display of the second terminal.

Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

Abstract: A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.

Abstract: A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Abstract: A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Abstract: A check valve includes a housing defining an inlet, an outlet, a passage between the inlet and outlet, and a sealing surface along the passage. A piston member is disposed about a longitudinal axis and has a sealing face disposed perpendicular to the longitudinal axis and a circular groove defined therein extending inward from the sealing face. An O-ring is disposed in the groove. A biasing member exerts a biasing force on the piston and thus forces the O-ring into sealing engagement with the sealing surface of the housing. The piston member is moveable from a first position in which the O-ring is sealingly engaged with the sealing surface of the housing and thus the outlet is sealed from the inlet, and a second position in which the O-ring is spaced from the sealing surface of the housing and thus the outlet is not sealed from the inlet.

Abstract: Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

Abstract: A check valve includes a housing defining an inlet, an outlet, a passage between the inlet and outlet, and a sealing surface along the passage. A piston member is disposed about a longitudinal axis and has a sealing face disposed perpendicular to the longitudinal axis and a circular groove defined therein extending inward from the sealing face. An O-ring is disposed in the groove. A biasing member exerts a biasing force on the piston and thus forces the O-ring into sealing engagement with the sealing surface of the housing. The piston member is moveable from a first position in which the O-ring is sealingly engaged with the sealing surface of the housing and thus the outlet is sealed from the inlet, and a second position in which the O-ring is spaced from the sealing surface of the housing and thus the outlet is not sealed from the inlet.

Abstract: An integrated circuit (IC) chip may include a first gate-all-around (GAA) device and a second GAA device. The first GAA device may include a first set of silicon dioxide structures around a first set of silicon channels, a first set of hafnium dioxide structures around the first set of silicon dioxide structures, and a first metal structure around the first set of hafnium dioxide structures. The second GAA device may include a second set of silicon dioxide structures around a second set of silicon channels, and a second metal structure around the second set of silicon dioxide structures. Each silicon dioxide structure in the first set of silicon dioxide structures may have a first thickness. Each silicon dioxide structure in the second set of silicon dioxide structures may have a second thickness, which is greater than the first thickness.

Abstract: A screen mirroring display method implemented by a first electronic device, where the method includes displaying a first display interface, receiving a screen mirroring instruction for projecting the first display interface onto a second electronic device, determining a first target control in the first display interface in response to the screen mirroring instruction, and sending a first message to the second electronic device, where the first message includes a drawing instruction of the first target control to prompt the second electronic device to draw a first screen mirroring interface according to the drawing instruction, where the first screen mirroring interface includes the first target control.

Abstract: A screen mirroring display method includes a destination device receiving a first message from a first source device and a second message from a second source device, where the first message includes a first drawing instruction. The first drawing instruction instructs the destination device to draw a first target control in a first interface displayed by the first source device. The second message includes a second drawing instruction. The second drawing instruction instructs the destination device to draw a second target control in a second interface displayed by the second source device. Then the destination device draws a screen mirroring interface according to the first drawing instruction and the second drawing instruction, where the screen mirroring interface includes the first target control and the second target control.

Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

Abstract: A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.

Abstract: A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.