Patents by Inventor Xi Wei

Xi Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230023073
    Abstract: An integrated circuit (IC) chip may include a first gate-all-around (GAA) device and a second GAA device. The first GAA device may include a first set of silicon dioxide structures around a first set of silicon channels, a first set of hafnium dioxide structures around the first set of silicon dioxide structures, and a first metal structure around the first set of hafnium dioxide structures. The second GAA device may include a second set of silicon dioxide structures around a second set of silicon channels, and a second metal structure around the second set of silicon dioxide structures. Each silicon dioxide structure in the first set of silicon dioxide structures may have a first thickness. Each silicon dioxide structure in the second set of silicon dioxide structures may have a second thickness, which is greater than the first thickness.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 26, 2023
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Robert B. Lefferts, Xi-Wei Lin, Munkang Choi
  • Publication number: 20220391161
    Abstract: A screen mirroring display method implemented by a first electronic device, where the method includes displaying a first display interface, receiving a screen mirroring instruction for projecting the first display interface onto a second electronic device, determining a first target control in the first display interface in response to the screen mirroring instruction, and sending a first message to the second electronic device, where the first message includes a drawing instruction of the first target control to prompt the second electronic device to draw a first screen mirroring interface according to the drawing instruction, where the first screen mirroring interface includes the first target control.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 8, 2022
    Inventors: Zhenhua Fan, Yuan Cao, Xi Wei
  • Publication number: 20220308823
    Abstract: A screen mirroring display method includes a destination device receiving a first message from a first source device and a second message from a second source device, where the first message includes a first drawing instruction. The first drawing instruction instructs the destination device to draw a first target control in a first interface displayed by the first source device. The second message includes a second drawing instruction. The second drawing instruction instructs the destination device to draw a second target control in a second interface displayed by the second source device. Then the destination device draws a screen mirroring interface according to the first drawing instruction and the second drawing instruction, where the screen mirroring interface includes the first target control and the second target control.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 29, 2022
    Inventors: Zhenhua Fan, Yuan Cao, Sucheng Bian, Wanyi Yang, Pengcheng Li, Xi Wei
  • Publication number: 20220172953
    Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 2, 2022
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Xi-Wei Lin
  • Publication number: 20220020646
    Abstract: A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 20, 2022
    Applicant: Synopsys, Inc.
    Inventors: Xi-Wei LIN, Victor MOROZ
  • Publication number: 20220020647
    Abstract: A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 20, 2022
    Applicant: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Victor Moroz
  • Patent number: 10927741
    Abstract: A method includes determining whether a urea refill event is detected, and clearing a quality accumulator value and clearing a latching abort command. The method includes determining whether urea fluid quality check abort conditions are met, and clearing the urea quality accumulator, latching the abort command, and exiting the reductant fluid quality check. In response to the abort conditions not being met, incrementing the urea quality accumulator according to an amount of urea being injected, and comparing the accumulated urea quantity to a low test threshold. The method includes, in response to the accumulated urea quantity being greater than the low test threshold, comparing the accumulated urea quantity to a high test threshold, and in response to the urea quantity being greater than the high test threshold, determining whether the a NOx exceedance is observed and clearing a urea quality error in response to the NOx exceedance not being observed.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 23, 2021
    Assignee: Cummins Emission Solutions Inc.
    Inventors: Xi Wei, David Samuel Everard, Baohua Qi, Mickey R. McDaniel, Edmund P. Hodzen, Guoqiang Li
  • Publication number: 20200370667
    Abstract: A refrigerant relief valve manifold includes a valve body assembly and a valve member. The valve body assembly defines a lower inlet and a plurality of upper outlets. The valve body assembly further defines a plurality of low pressure drop passages. Each valve body assembly low pressure drop passage extends between the lower inlet and an associated upper outlet. The valve member is movably disposed in the valve body assembly. The valve member defines a plurality of low pressure drop passages. The valve body assembly further includes a plurality of true mountings. Each valve body assembly true mounting defining one the upper outlet. Each valve body assembly true mounting is structured to be coupled to a coupled element such as, but not limited to, a relief valve.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Applicant: Mueller Refrigeration, LLC
    Inventors: Mark Bornand, Shi Xi Wei
  • Patent number: 10482212
    Abstract: Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 19, 2019
    Assignee: Synopsys, Inc.
    Inventors: Zudian Qin, Karim El Sayed, Victor Moroz, Xi-Wei Lin
  • Patent number: 10428654
    Abstract: A cutter head has a front surface formed with several transmitting ports, a protection plate mounted at an external-end hole of each port, several microwave generating mechanisms distributed in two manners: first, the generating mechanisms are uniformly arranged in the cutter head; second, the microwave generating mechanisms in the same number as hobbing cutters. Each generating mechanism includes a microwave source, a magnetron, a rectangular waveguide, a circulator and a microwave focus radiator, wherein the microwave source is connected with the magnetron, the magnetron is connected with one end of the waveguide, the other end of the waveguide is connected with a first port of the circulator, a second port of the circulator is connected with the microwave focus radiator, and a water load is connected to a third port of the circulator. The focus radiator includes a standard waveguide section, an impedance matching section and a compressed radiation section.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: October 1, 2019
    Assignee: NORTHEASTERN UNIVERSITY
    Inventors: Xia Ting Feng, Gao Ming Lu, Yuan Hui Li, Xi Wei Zhang
  • Patent number: 10365193
    Abstract: An apparatus and method for determining time-dependence failure under constant temperature through high pressure true triaxial loading for hard rock, includes a pressure chamber and four actuators, wherein a sample bearing platform is arranged in a center of the pressure chamber, a sample bearing and containing chamber is arranged in a center of the sample bearing platform, and a confining pressure loading oil supply hole is formed in the sample bearing platform, and communicates with a confining pressure loading injection pump; each actuator includes a sealing cover, an annular end cover, a counter-force cylinder barrel, a piston, a piston rod, a sealing flange and a stress loading injection pump; a heating coil is arranged in the pressure chamber; a force sensor is fixedly mounted at the end part of the piston rod; and a pressure sensor is mounted in the sample bearing platform.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: July 30, 2019
    Assignee: NORTHEASTERN UNIVERSITY
    Inventors: Xia ting Feng, Xi wei Zhang, Cheng xiang Yang, Shuai Peng, Jun Tian, Rui Kong, Dong hui Ma
  • Patent number: 10324014
    Abstract: A high-pressure true triaxial test apparatus with capacity of low-frequency disturbance and high-speed impact includes static and dynamic loading frames, four static loading actuators, two dynamic loading actuators and an SHPB mechanism, wherein all actuators are connected with a hydraulic station system; a hollow way is formed in the axial center of each piston shaft of the dynamic loading actuators, a dynamic pressure sensor adopting a hollow ring structure is mounted at the end part of each piston shaft, and the SHPB mechanism applies a high-speed impact load on a rock sample through the dynamic pressure sensors respectively; and the dynamic loading actuators adopt a static pressure oilway balance support sealing manner and are connected with the hydraulic station system, each oilway is provided with an energy accumulator, and flow is increased by the servo valves to drive pistons to perform dynamic response.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: June 18, 2019
    Assignee: NORTHEASTERN UNIVERSITY
    Inventors: Xia ting Feng, Xi wei Zhang, Rui Kong, Cheng xiang Yang, Dong hui Ma, Shuai Peng, Lei Shi, Zhi bin Yao, Jun Tian
  • Publication number: 20190178133
    Abstract: A method includes determining whether a urea refill event is detected, and clearing a quality accumulator value and clearing a latching abort command. The method includes determining whether urea fluid quality check abort conditions are met, and clearing the urea quality accumulator, latching the abort command, and exiting the reductant fluid quality check. In response to the abort conditions not being met, incrementing the urea quality accumulator according to an amount of urea being injected, and comparing the accumulated urea quantity to a low test threshold. The method includes, in response to the accumulated urea quantity being greater than the low test threshold, comparing the accumulated urea quantity to a high test threshold, and in response to the urea quantity being greater than the high test threshold, determining whether the a NOx exceedance is observed and clearing a urea quality error in response to the NOx exceedance not being observed.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 13, 2019
    Inventors: Xi Wei, David Samuel Everard, Baohua Qi, Mickey R. McDaniel, Edmund P. Hodzen, Guoquian Li
  • Patent number: 10311200
    Abstract: Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 4, 2019
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Karim El Sayed, Terry Sylvan Kam-Chiu Ma, Xi-Wei Lin, Qiang Lu
  • Patent number: 10306465
    Abstract: Managing data security on a mobile device. Data associated with a mobile device is received; the data includes an identification (ID) of the mobile device and a location of the mobile device relative to one or more location sensor devices. A path is determined, relative to the one or more location sensor devices, through which the mobile device has traveled. An electronic security key is communicated to the mobile device based on determining that the path corresponds to a defined path associated with the mobile device.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ye Chen, Ruomeng Hao, Ting Jiang, Ning Wang, Shu Xi Wei, Youmiao Zhang
  • Publication number: 20190040741
    Abstract: A cutter head has a front surface formed with several transmitting ports, a protection plate mounted at an external-end hole of each port, several microwave generating mechanisms distributed in two manners: first, the generating mechanisms are uniformly arranged in the cutter head; second, the microwave generating mechanisms in the same number as hobbing cutters. Each generating mechanism includes a microwave source, a magnetron, a rectangular waveguide, a circulator and a microwave focus radiator, wherein the microwave source is connected with the magnetron, the magnetron is connected with one end of the waveguide, the other end of the waveguide is connected with a first port of the circulator, a second port of the circulator is connected with the microwave focus radiator, and a water load is connected to a third port of the circulator. The focus radiator includes a standard waveguide section, an impedance matching section and a compressed radiation section.
    Type: Application
    Filed: June 9, 2017
    Publication date: February 7, 2019
    Applicant: NORTHEASTERN UNIVERSITY
    Inventors: Xia Ting FENG, Gao Ming LU, Yuan Hui LI, Xi Wei ZHANG
  • Patent number: 10196955
    Abstract: A method includes determining whether a urea refill event is detected, and clearing a quality accumulator value and clearing a latching abort command. The method includes determining whether urea fluid quality check abort conditions are met, and clearing the urea quality accumulator, latching the abort command, and exiting the reductant fluid quality check. In response to the abort conditions not being met, incrementing the urea quality accumulator according to an amount of urea being injected, and comparing the accumulated urea quantity to a low test threshold. The method includes, in response to the accumulated urea quantity being greater than the low test threshold, comparing the accumulated urea quantity to a high test threshold, and in response to the urea quantity being greater than the high test threshold, determining whether the a NOx exceedance is observed and clearing a urea quality error in response to the NOx exceedance not being observed.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: February 5, 2019
    Assignee: Cummins Emission Solutions Inc.
    Inventors: Xi Wei, David Samuel Everard, Baohua Qi, Mickey R. McDaniel, Edmund P. Hodzen, Guoquian Li
  • Publication number: 20180313727
    Abstract: An apparatus and method for determining time-dependence failure under constant temperature through high pressure true triaxial loading for hard rock, includes a pressure chamber and four actuators, wherein a sample bearing platform is arranged in a center of the pressure chamber, a sample bearing and containing chamber is arranged in a center of the sample bearing platform, and a confining pressure loading oil supply hole is formed in the sample bearing platform, and communicates with a confining pressure loading injection pump; each actuator includes a sealing cover, an annular end cover, a counter-force cylinder barrel, a piston, a piston rod, a sealing flange and a stress loading injection pump; a heating coil is arranged in the pressure chamber; a force sensor is fixedly mounted at the end part of the piston rod; and a pressure sensor is mounted in the sample bearing platform.
    Type: Application
    Filed: January 17, 2017
    Publication date: November 1, 2018
    Inventors: Xia ting FENG, Xi wei ZHANG, Cheng xiang YANG, Shuai PENG, Jun TIAN, Rui KONG, Dong hui MA
  • Publication number: 20180275034
    Abstract: A high-pressure true triaxial test apparatus with capacity of low-frequency disturbance and high-speed impact includes static and dynamic loading frames, four static loading actuators, two dynamic loading actuators and an SHPB mechanism, wherein all actuators are connected with a hydraulic station system; a hollow way is formed in the axial center of each piston shaft of the dynamic loading actuators, a dynamic pressure sensor adopting a hollow ring structure is mounted at the end part of each piston shaft, and the SHPB mechanism applies a high-speed impact load on a rock sample through the dynamic pressure sensors respectively; and the dynamic loading actuators adopt a static pressure oilway balance support sealing manner and are connected with the hydraulic station system, each oilway is provided with an energy accumulator, and flow is increased by the servo valves to drive pistons to perform dynamic response.
    Type: Application
    Filed: March 28, 2017
    Publication date: September 27, 2018
    Inventors: Xia ting FENG, Xi wei ZHANG, Rui KONG, Cheng xiang YANG, Dong hui MA, Shuai PENG, Lei SHI, Zhi bin YAO, Jun TIAN
  • Publication number: 20180239857
    Abstract: Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 23, 2018
    Applicant: Synopsys, Inc.
    Inventors: Zudian Qin, Karim El Sayed, Victor Moroz, Xi-Wei Lin