Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

Abstract: Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.

Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

Abstract: Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior caused by the thermal cycles of the wire, vias, and insulators comprising the BEOL materials is simulated. Extraction of the integrated circuit structural information, regarding the BEOL materials, yields anisotropic information. Layout-dependent material volume fractions are computed using integrated circuit structural information. Anisotropic mechanical properties are determined based on the structural information.

Abstract: Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior caused by the thermal cycles of the wire, vias, and insulators comprising the BEOL materials is simulated. Extraction of the integrated circuit structural information, regarding the BEOL materials, yields anisotropic information. Layout-dependent material volume fractions are computed using integrated circuit structural information. Anisotropic mechanical properties are determined based on the structural information.

Abstract: Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.

Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.

Abstract: A data storage system, and a method for accessing data in a data storage system, wherein the data storage system comprises at least a first volume and a second volume, and the first volume and the second volume remain consistent by a synchronous copy relationship, the method comprising: setting a virtual unique identifier of the second volume as a unique identifier of the first volume; creating a first path from a host to the first volume and a second path from the host to the second volume by using the unique identifier of the first volume; accessing data by using the first path from the host to the first volume; and setting the second path from the host to the second volume as unavailable.

Abstract: A method includes determining whether a urea refill event is detected, and clearing a quality accumulator value and clearing a latching abort command. The method includes determining whether urea fluid quality check abort conditions are met, and clearing the urea quality accumulator, latching the abort command, and exiting the reductant fluid quality check. In response to the abort conditions not being met, incrementing the urea quality accumulator according to an amount of urea being injected, and comparing the accumulated urea quantity to a low test threshold. The method includes, in response to the accumulated urea quantity being greater than the low test threshold, comparing the accumulated urea quantity to a high test threshold, and in response to the urea quantity being greater than the high test threshold, determining whether the a NOx exceedance is observed and clearing a urea quality error in response to the NOx exceedance not being observed.

Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.

Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: A system is provided for controlling an air handling system for an internal combustion engine. A dual-stage turbocharger includes a high-pressure compressor and variable geometry turbine combination fluidly coupled to a low-pressure compressor and variable geometry turbine combination. A control circuit includes a memory having instructions stored therein that are executable by the control circuit to determine a target low-pressure compressor ratio, a target high-pressure compressor ratio, a target high-pressure compressor inlet temperature and a target high-pressure compressor inlet pressure as a function of a target outlet pressure of the high-pressure compressor and a temperature, a pressure and a target flow rate of air entering the air inlet of the low-pressure compressor, and to control the geometries of the low-pressure and high-pressure turbines as a function of the target low-pressure compressor ratio the target high-pressure compressor ratio respectively.

Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: A system is provided for controlling an air handling system for an internal combustion engine. A dual-stage turbocharger includes a high-pressure compressor and variable geometry turbine combination fluidly coupled to a low-pressure compressor and variable geometry turbine combination. A control circuit includes a memory having instructions stored therein that are executable by the control circuit to determine a target low-pressure compressor ratio, a target high-pressure compressor ratio, a target high-pressure compressor inlet temperature and a target high-pressure compressor inlet pressure as a function of a target outlet pressure of the high-pressure compressor and a temperature, a pressure and a target flow rate of air entering the air inlet of the low-pressure compressor, and to control the geometries of the low-pressure and high-pressure turbines as a function of the target low-pressure compressor ratio the target high-pressure compressor ratio respectively.

Abstract: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

Abstract: A method includes interpreting a powertrain load variation amplitude and an internal combustion engine output profile. The method further includes determining an engine output differential in response to the powertrain load variation amplitude and the internal combustion engine output profile. The method further includes providing an energy accumulator sizing parameter and/or an alternate motive power provider sizing parameter in response to the engine output differential.

Abstract: A system includes a hybrid drive system having an internal combustion engine and a non-combustion motive power source. The system includes an energy storage system and a controller. The controller is structured to functionally execute operations to improve an efficiency of they hybrid drive system. The controller interprets duty cycle data, a boundary condition, and an optimization criterion. The controller further elects a load response operating condition in response to the duty cycle data, the boundary condition, and the optimization criterion. The controller adjusts the operation of the engine and/or the motive power source in response to the elected load response operating condition.

Abstract: An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.