Abstract: A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.

Abstract: A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.

Abstract: Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

Abstract: Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

Abstract: A method of forming an electrical connection between a buried power rail (BPR) of an unfinished complementary field effect transistor (CFET) and a source or drain epitaxial growth of a lower level of the CFET is provided. The method includes performing silicon epitaxial growth in a lower level of the CFET, adding a contact material to a portion of an exposed portion of the silicon epitaxial growth in the lower level, the exposed portion of the silicon epitaxial growth being located in a vertical slot of the unfinished CFET structure, adding a conductive material within a vertical channel, the conductive material being in contact with the added contact material and the BPR to form an electrical connection between the portion of the exposed portion of the silicon epitaxial growth and the BPR and etching back a portion of the added conductive material within the vertical channel.

Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

Abstract: A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.

Abstract: A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Abstract: A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Abstract: Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

Abstract: An integrated circuit (IC) chip may include a first gate-all-around (GAA) device and a second GAA device. The first GAA device may include a first set of silicon dioxide structures around a first set of silicon channels, a first set of hafnium dioxide structures around the first set of silicon dioxide structures, and a first metal structure around the first set of hafnium dioxide structures. The second GAA device may include a second set of silicon dioxide structures around a second set of silicon channels, and a second metal structure around the second set of silicon dioxide structures. Each silicon dioxide structure in the first set of silicon dioxide structures may have a first thickness. Each silicon dioxide structure in the second set of silicon dioxide structures may have a second thickness, which is greater than the first thickness.

Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

Abstract: A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.

Abstract: A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.

Abstract: Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation.

Abstract: Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.

Abstract: Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation.

Abstract: Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.

Abstract: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

Abstract: A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where the potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of the integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.