Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

Abstract: A local interconnect structure that includes a silicon spacer. After deposition of polysilicon gates and formation of spacers on a semiconductor substrate, photolithography and oxide etch steps are performed to remove a portion of a spacer along a segment of the gate where local interconnection is to be formed. A thin screen oxide layer is deposited over the wafer, followed by the formation of diffusion regions. A silicon layer (either amorphous or polycrystalline) is then deposited. The silicon layer is then selectively etched so as to form a silicon spacer along the segment of the gate where local interconnection is to be formed. A conventional SALICIDE process is performed, leading to simultaneous silicidation of the diffusion region, the gate, and the silicon spacer. The resulting local interconnect electrically connects the gate and the diffusion region.

Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

Abstract: A semiconductor manufacturing process is used to develop capacitors in compact areas such as at or near the interconnect level. According to one example embodiment, a substrate having a first and second conductor is separated by a dielectric, once the dielectric is removed a trench is formed, and a first material including silicon nitride is deposited over the substrate so that it covers the trench. A second material, including metal, is then deposited over the first material, covering it and the first and second conductors. CMP is then used to remove the metal over the field and isolate the filled metal from adjacent metals causing the silicon nitride to act as a natural CMP etch-stopper and protecting other areas of the interconnect from damage by the CMP.

Abstract: A technique for self-aligned processing of semiconductor device features is disclosed. This technique includes the formation of a semiconductor device with transistor gates having a polysilicon member that extends from the plane of a semiconductor substrate. A coating is deposited on the gates and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a polysilicon surface of the gates without lithographic processing. A recess is formed in the exposed polysilicon surface and at least partially filled with an etch stop material such as silicon nitride. Silicidation of the polysilicon member to form a silicide layer in the recess or a selective chemical vapor deposition on the bottom of the recess with an appropriate metal may be performed before filling the recess with the etch stop material.

Abstract: The relative sense of parallel propagating signals is inverted so reduce maximum transit time and transit-time variance. An integrated circuit comprises adjacent parallel signal paths, each extending from a respective driver to a respective load. Each signal path includes sense-inverting buffers and sense-preserving buffers arranged so that each sense-inverting buffer on one signal line is immediately adjacent to a sense-preserving buffer of the neighboring signal path. Signals co-propagating along the two signal paths have their relative senses inverted at each inter-path pair of adjacent buffers. As a result the crosstalk-induced tendencies of same-direction transitions to accelerate transition and opposing-direction transitions to retard transitions compensate for each other. In this way, the arrangement of sense-inverting and sense-preserving buffers reduces the maximum propagation delay across the signal paths and reduces the variance in propagation delays.

Abstract: In a dual-damascene method for forming an integrated circuit with copper conductors, a fluorinated silicon oxide (SiOF) marker layer is formed between an intermetal silicon dioxide layer and an upper silicon dioxide layer. A plasma etch forms trenches (as sited for future copper conductors) in the upper silicon dioxide layer according to a pattern defined by a photoresist mask. During this trench etch, the spectral characteristics of the plasma are monitored. After the marker layer is exposed and etching of the SiOF begins, an optical spectral detector detect is an enhancement of a spectral signal associated with fluorine ions. This detection is used in determining when to terminate the trench etch. A further photolithographic step results in via apertures. The trenches are then filled with copper. The resulting structure includes marker material in areas protected by the trench etch mask. However, because the dielectric constant of fluorinated silicon oxide (k=3.3-3.

Abstract: The relative sense of parallel propagating signals is inverted so reduce maximum transit time and transit-time variance. An integrated circuit comprises adjacent parallel signal paths, each extending from a respective driver to a respective load. Each signal path includes sense-inverting buffers and sense-preserving buffers arranged so that each sense-inverting buffer on one signal line is immediately adjacent to a sense-preserving buffer of the neighboring signal path. Signals co-propagating along the two signal paths have their relative senses inverted at each inter-path pair of adjacent buffers. As a result the crosstalk-induced tendencies of same-direction transitions to accelerate transition and opposing-direction transitions to retard transitions compensate for each other. In this way, the arrangement of sense-inverting and sense-preserving buffers reduces the maximum propagation delay across the signal paths and reduces the variance in propagation delays.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

Abstract: Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and a drain region of the substrate are doped, with the first and second spacers correspondingly masking first and second regions of the substrate. The first and second spacers are removed after doping and the first and second regions are exposed. The exposed first and second regions are then doped. The substrate is heated after this second doping stage to simultaneously activate dopant in the source region, the drain region, the first region, and the second region. A third spacer is then formed on the first region and a fourth spacer is then formed on the second region. A suicide contact is established with at least the transistor member, the source region, or the drain region after formation of the third and fourth spacers.

Abstract: After a metal deposition preclean, a very thin titanium layer is deposited followed by a thick nickel layer on a semiconductor silicon substrate. The titanium and nickel are deposited sequentially in a vacuum cluster tool to prevent oxidation of titanium in air. The silicon substrate and the metal layers are subject to a relatively low temperature anneal. The annealing causes the titanium to act as a reductant to break up the residual surface oxide on the surface of the silicon substrate and allows the nickel to react with the silicon substrate to form nickel silicide.

Abstract: A semiconductor manufacturing process is used to develop capacitors in compact areas such as at or near the interconnect level. According to one example embodiment, a substrate having a first and second conductor is separated by a dielectric, once the dielectric is removed a trench is formed, and a first material including silicon nitride is deposited over the substrate so that it covers the trench. A second material, including metal, is then deposited over the first material, covering it and the first and second conductors. CMP is then used to remove the metal over the field and isolate the filled metal from adjacent metals causing the silicon nitride to act as a natural CMP etch-stopper and protecting other areas of the interconnect from damage by the CMP.

Abstract: An integrated circuit workpiece is provided having a polysilicon transistor gate member extending from a substrate. A pair of oxide spacers are formed on opposing sides of the gate member and a metal layer is deposited on the workpiece. The workpiece is heated to form a silicide region on the gate member and on selected regions of the substrate. A surface profile for each of the spacers is provided which has a progressively steeper slope from a rounded upper shoulder portion to a lower wall portion to control thickness of the metal layer on the gate member relative to thickness on the spacers. Formation of the spacers may include plasma etching with a gas mixture having from about 1 to about 20% molecular oxygen to steepen a slope of the surface profile of each of the spacers. Further, shaping of the spacers may be utilized to establish a ratio of the minimum thickness on the gate member to the minimum thickness on each spacer of at least about 2.5 to reduce silicide bridging of the spacers.

Abstract: A semiconductor manufacturing process is used to develop capacitors in compact areas such as at or near the interconnect level. According to one example embodiment, a substrate having a first and second conductor is separated by a dielectric, once the dielectric is removed a trench is formed, and a first material including silicon nitride is deposited over the substrate so that it covers the trench. A second material, including metal, is then deposited over the first material, covering it and the first and second conductors. CMP is then used to remove the metal over the field and isolate the filled metal from adjacent metals causing the silicon nitride to act as a natural CMP etch-stopper and protecting other areas of the interconnect from damage by the CMP.

Abstract: Copper is the bulk interconnect metal in the manufacture of an integrated circuit in accordance with the damascene process. When copper is exposed through via apertures, carbon monoxide and hydrogen are used as reduction agents to convert black copper oxide to red copper oxide and the red copper oxide to copper. The integrated circuit is then transferred in a high vacuum to a sputter chamber so that re-oxidation does not occur before tantalum barrier metal can be deposited. As a result, a good tantalum-copper electrical contact can be made without risking embedding copper in oxide sidewalls (whence it could migrate to active circuit regions and impair device reliability).

Abstract: A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.

Abstract: An integrated circuit is disclosed that includes a semiconductor substrate, an oxide layer on the substrate, and a polysilicon layer on the oxide layer. The polysilicon layer extends away from the substrate and is doped with elemental boron to increase electrical conductivity thereof. Boron difluoride atoms are implanted in the substrate to define corresponding source and drain regions. Initially, the boron difluoride ions also penetrate a portion of the polysilicon layer. At least a portion of the polysilicon layer is removed to substantially reduce the fluorine-induced migration of boron through the oxide layer to the substrate.

Abstract: A local interconnect structure that includes a silicon spacer. After deposition of polysilicon gates and formation of spacers on a semiconductor substrate, photolithography and oxide etch steps are performed to remove a portion of a spacer along a segment of the gate where local interconnection is to be formed. A thin screen oxide layer is deposited over the wafer, followed by the formation of diffusion regions. A silicon layer (either amorphous or polycrystalline) is then deposited. The silicon layer is then selectively etched so as to form a silicon spacer along the segment of the gate where local interconnection is to be formed. A conventional SALICIDE process is performed, leading to simultaneous silicidation of the diffusion region, the gate, and the silicon spacer. The resulting local interconnect electrically connects the gate and the diffusion region.