Patents by Inventor Xi-Wei Lin
Xi-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9147027Abstract: A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.Type: GrantFiled: June 27, 2014Date of Patent: September 29, 2015Assignee: Synopsys, Inc.Inventors: Xi-Wei Lin, Ankush Oberai
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Publication number: 20150143306Abstract: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.Type: ApplicationFiled: December 29, 2014Publication date: May 21, 2015Applicant: SYNOPSYS, INC.Inventors: Victor Moroz, Xi-Wei Lin
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Publication number: 20150113492Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.Type: ApplicationFiled: December 26, 2014Publication date: April 23, 2015Applicant: SYNOPSYS, INC.Inventors: Xi-Wei Lin, Victor Moroz
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Patent number: 8964453Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.Type: GrantFiled: June 27, 2013Date of Patent: February 24, 2015Assignee: Synopsys, Inc.Inventors: Xi-Wei Lin, Victor Moroz
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Publication number: 20150041921Abstract: Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.Type: ApplicationFiled: September 19, 2014Publication date: February 12, 2015Applicant: SYNOPSYS, INC.Inventors: Munkang Choi, Victor Moroz, Xi-Wei Lin
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Publication number: 20150007121Abstract: A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.Type: ApplicationFiled: June 27, 2014Publication date: January 1, 2015Inventors: Xi-Wei Lin, Ankush Oberai
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Patent number: 8869078Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.Type: GrantFiled: April 9, 2014Date of Patent: October 21, 2014Assignee: Synopsys, Inc.Inventors: Victor Moroz, Munkang Choi, Xi-Wei Lin
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Patent number: 8847324Abstract: Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.Type: GrantFiled: December 17, 2012Date of Patent: September 30, 2014Assignee: Synopsys, Inc.Inventors: Munkang Choi, Victor Moroz, Xi-Wei Lin
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Publication number: 20140223395Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicant: Synopsys, Inc.Inventors: Victor Moroz, Munkang Choi, Xi-Wei Lin
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Publication number: 20140208280Abstract: Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior caused by the thermal cycles of the wire, vias, and insulators comprising the BEOL materials is simulated. Extraction of the integrated circuit structural information, regarding the BEOL materials, yields anisotropic information. Layout-dependent material volume fractions are computed using integrated circuit structural information. Anisotropic mechanical properties are determined based on the structural information.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Applicant: SYNOPSYS, INC.Inventors: Xiaopeng Xu, Dasarapu Vinay Kumar, Xi-Wei Lin
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Patent number: 8776005Abstract: Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior caused by the thermal cycles of the wire, vias, and insulators comprising the BEOL materials is simulated. Extraction of the integrated circuit structural information, regarding the BEOL materials, yields anisotropic information. Layout-dependent material volume fractions are computed using integrated circuit structural information. Anisotropic mechanical properties are determined based on the structural information.Type: GrantFiled: January 18, 2013Date of Patent: July 8, 2014Assignee: Synopsys, Inc.Inventors: Xiaopeng Xu, Dasarapu Vinay Kumar, Xi-Wei Lin
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Publication number: 20140167174Abstract: Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Inventors: Munkang Choi, Victor Moroz, Xi-Wei Lin
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Patent number: 8701054Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.Type: GrantFiled: September 20, 2011Date of Patent: April 15, 2014Assignee: Synopsys, Inc.Inventors: Victor Moroz, Munkang Choi, Xi-Wei Lin
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Patent number: 8694942Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.Type: GrantFiled: July 8, 2013Date of Patent: April 8, 2014Assignee: Synopsys, Inc.Inventors: Xi-Wei Lin, Jyh-Chwen Frank Lee, Dipankar Pramanik
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Patent number: 8686512Abstract: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.Type: GrantFiled: August 30, 2011Date of Patent: April 1, 2014Assignee: Synopsys, Inc.Inventors: Victor Moroz, Dipankar Pramanik, Xi-Wei Lin
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Publication number: 20140003133Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.Type: ApplicationFiled: June 27, 2013Publication date: January 2, 2014Applicant: Synopsys, Inc.Inventors: Xi-Wei Lin, Victor Moroz
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Publication number: 20130332893Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.Type: ApplicationFiled: July 8, 2013Publication date: December 12, 2013Inventors: Xi-Wei Lin, Jyh-Chwen Frank Lee, Dipankar Pramanik
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Patent number: 8504969Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.Type: GrantFiled: December 7, 2010Date of Patent: August 6, 2013Assignee: Synopsys, Inc.Inventors: Xi-Wei Lin, Jyh-Chwen Frank Lee, Dipankar Pramanik
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Publication number: 20120280354Abstract: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Applicant: SYNOPSYS, INC.Inventors: VICTOR MOROZ, XI-WEI LIN
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Patent number: 8219961Abstract: An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.Type: GrantFiled: May 20, 2011Date of Patent: July 10, 2012Assignee: Synopsys, Inc.Inventors: Victor Moroz, Dipankar Pramanik, Kishore Singhal, Xi-Wei Lin