Abstract: An apparatus is provided that includes a NAND string including a first memory cell coupled to a first word line, and a control circuit coupled to the NAND string. The control circuit is configured to apply a verify voltage to the first word line, perform a verify test on the first memory cell to sense a hole conduction current, and perform a program operation on the first memory cell without performing a pre-charge operation.

Abstract: The memory device includes a memory block with a source line, a plurality of bit lines, and an array of memory cells that are disposed between the source line and the plurality of bit lines. The memory cells are arranged in a plurality of word lines, which are divided into at least three sub-blocks including a source-side sub-block, a drain-side sub-block, and at least one middle sub-block. The memory device also includes circuitry for programming the memory cells of the memory block. The circuitry is configured to program the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution that includes two data states. The circuitry is also configured to program the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution that is different than the first SLC threshold voltage distribution.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes defining channels. The memory cells form a block including a first sub-block and a second sub-block disposed vertically above the first sub-block. A control means is configured to pre-charge the channels of the memory holes in a pre-charge operation. The control means applies each of a series of programming pulses of a program voltage in a program phase followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines in a verify phase to program and verify the memory cells connected thereto during program loops. The pre-charge operation for the second sub-block occurs during the verify phase of a previously occurring one of the plurality of program loops.

Abstract: A memory apparatus includes memory cells configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to detect whether data stored in a group of the memory cells as one bit per each of the memory cells has errors. The control means is also configured to bypass error correction of the data stored in the group of the memory cells in response to not detecting the errors in the data stored.

Abstract: A non-volatile memory system performs a sensing process for memory cells by sensing the memory cells multiple times to achieve multiple results for determining whether the memory cells are in a particular condition (e.g., a memory cell current distribution) in response to a same reference signal without adjusting the memory cell between the multiple times. The memory system determines whether the memory cells are in the particular condition based on whether a majority of the multiple results indicate that the memory cells are in the particular condition. In one embodiment, the system programs weight information into the non-volatile memory cells and performs vector-matrix multiplication using the weight information programmed in the non-volatile memory cells. The sensing the memory cells multiple times to achieve multiple results can be performed as part of a program verify process when programming weight information and/or as part of the vector-matrix multiplication.

Abstract: A memory apparatus includes memory cells connected to word lines and disposed in memory holes extending vertically through a stack of the word lines. The memory cells form a block including a first sub-block vertically below a second sub-block. A control means is configured to determine a vertical location of a selected one of the word lines connected to the memory cells being programmed in a program operation. The control means applies at least one programming pulse to the selected one of the word lines to program the memory cells connected thereto while applying ones of a plurality of pass voltages to unselected ones of the word lines of the second sub-block during the program operation. The one of the plurality of pass voltages used for each of the unselected ones of the word lines is based on the vertical location of the selected one of the word lines.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines and a plurality of NAND strings. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines to a plurality of data states in a plurality of program loops that include programming pulses and verify operations. During at least one of the verify operations, the circuitry is configured to not lock out a set of the plurality of NAND strings. The NAND strings of the set include at least some of the memory cells of the selected word line that have completed programming so that electricity is conducted through the NAND strings of the set during sensing.

Abstract: A memory apparatus includes memory cells connected to word lines and disposed in memory holes extending vertically through a stack of the plurality of word lines. The memory cells are configured to retain a threshold voltage and form a block including a first sub-block and a second sub-block to define an interface region therebetween. The word lines include dummy word lines disposed adjacent the interface region. A control means is configured to erase the memory cells. The control means is also configured to read the threshold voltage of the memory cells connected to one or more of the dummy word lines and adjust based on the threshold voltage of the memory cells connected to one or more of the dummy word lines relative to a dummy target voltage and based on which of the one of the first sub-block and the second sub-block is erased in the erase operation.

Abstract: A memory apparatus includes memory cells each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to read a subset of the memory cells using only one detect read voltage during a detect read operation prior to a read operation and count a detect bit count of one of the memory cells having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage. The control means is also configured to read the memory cells using at least one adjusted read level for at least one of the plurality of data states during the read operation. The at least one adjusted read level is based on the detect bit count.

Abstract: A method for treating a microsatellite-stable (MSS) solid tumor is provided. The method includes administering a therapeutically effective amount of icariside I to a subject suffering from the MSS solid tumor. The method further includes administering a combination anti-cancer active agent to the subject, the combination anti-cancer active agent includes an immunotherapeutic agent (for example, a PD-1/PD-L1 inhibitor and/or a CAR-T therapy product). A use of the icariside I in the preparation of a drug for treating or preventing the MSS solid tumor, particularly a MSS gastric cancer, a MSS intestinal cancer, a MSS lung cancer, a MSS pancreatic cancer, and a MSS hepatocellular carcinoma, and a kit including the same are further provided. A use of a combination of the icariside I and the immunotherapeutic agent in the preparation of a drug for treating or preventing the MSS solid tumor.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.

Abstract: Technology for programming memory cell transistors to operation region dependent current states. The memory cell transistors may include NAND memory cells. Programming memory cell transistors to a current state may include applying a programming voltage to control gates of the respective memory cells transistor and then verifying the respective memory cells. Verifying may include applying a verify reference voltage to the memory cell transistors and testing their respective currents with respect to a target current state. The same verify reference voltage may be used for all current states. The spacing between the current states depends on whether the memory cell transistor is operating in the sub-threshold region or linear region. The spacing between current states in the linear region may be linear; however, the spacing between current states in the sub-threshold region may be exponential. In-memory compute may be performed using the programmed memory cells.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state. The memory cells in both the erased data state and in the programmed data state have threshold voltages Vt that are less than 0 V.

Abstract: A memory apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to convert user data into joint data states comprising one of the plurality of data states for each of the memory cells of pairs of the memory cells and representing a quantity of bits according to a dual-cell encoding scheme. At least some of the plurality of data states of each of the memory cells of the pairs are not used in the dual-cell encoding scheme with ones of the plurality of data states not used for one of the memory cells of the pairs being different than ones of the plurality of data states not used for another of the memory cells of the pairs. The control means also stores the user data using the memory cells of the pairs.

Abstract: A non-volatile memory is divided into multiple zones of non-volatile memory cells. During a sensing operation that includes concurrently sensing total output current from a bit line while the bit line is concurrently receiving output current from multiple non-volatile memory cells that are in different zones, different voltages are applied to selected word lines in different zones based on how far a respective zone is from the bit line driver.

Abstract: Technology is disclosed herein for a storage system and method for multi-stage discharge of a read pass voltage. In an aspect, the voltage on unselected word lines is reduced from the read pass voltage to an intermediate voltage during a first stage near the end of a read operation. A read reference voltage on the selected word line may be changed (e.g., increased) to the intermediate voltage during the first stage. During a second stage the voltage on the unselected word lines may be reduced from the intermediate voltage to a final voltage. The voltage on the selected word line may also be decreased during the second stage from the intermediate voltage to the final voltage. The multi-stage discharge of the read pass voltage may reduce peak current consumption (e.g., peak Icc) in a final portion of the read operation.

Abstract: A memory apparatus includes memory cells connected to word lines and operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is coupled to the word lines and is configured to program the memory cells in a program operation. Following programming of the memory cells connected to specific ones of the word lines, the control means is also configured to apply a predetermined dummy read voltage to the specific ones of the word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the word lines determined based on an amount of the memory cells that are programmed.

Abstract: The memory device includes a memory block with memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry for optimizing a plurality of read voltages that are associated with a plurality of data states. With a first set of parameters, the circuitry performs a first threshold voltage tracking operation on a selected word line of the plurality of word lines to establish an optimized read voltage for a first data state of the plurality of data states. The circuitry then establishes a second set of parameters as a function of results of the first threshold voltage tracking operation. With the second set of parameters, the circuitry performs a second threshold voltage tracking operation on the selected word line to establish an optimized read voltage for a second data state of the plurality of data states.

Abstract: A non-volatile storage apparatus continuously maintains unselected word lines for multiple regions in multiple blocks at one or more overdrive voltages and continuously maintains unselected select lines for multiple regions in multiple blocks at one or more unselected voltages while performing a read process for non-volatile memory cells in one or more regions of one or more blocks of the same die, without lowering those signals to ground or another resting voltage. Selected word lines are separately temporarily toggled to a read reference voltage to enable reading and then reverted back to an overdrive voltage upon completion of the reading. Selected select lines are separately temporarily toggled to a select voltage to enable reading and then reverted back to an unselected voltage upon completion of the reading.

Abstract: A memory device that has a memory block with a plurality of word lines is provided. The memory device also includes circuitry that is configured to read data in a selected word line. The circuitry sets a reference voltage at a reduced voltage that is less than a default voltage and applies the reference voltage to the selected word line and performs a first read operation on the selected word line. In response to the first read operation passing, the circuitry is outputs data to a user. In response to the first read operation not passing, the circuitry sets the reference voltage at the default voltage and applies the reference voltage to the selected word line of the plurality of word lines and performs a second read operation on the selected word line.