Abstract: Provided are a distributed collaborative privacy calculation method and system for carbon emission in a plurality of power grids. An electricity quantity exchange matrix between regions, and a power generation information matrix, an electricity quantity exchange matrix, and a power-generation carbon emission information matrix of each region are constructed. A corresponding electricity carbon flow information matrix is calculated based on the power generation information matrix and the electricity quantity exchange matrix of each region. An electricity carbon emission balance equation is constructed, and an electricity carbon emission factor matrix of each region is calculated, where the electricity carbon emission factor matrix is constituted by an electricity carbon emission factor of a sub-region.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes. The control means is configured to apply a plurality of pulses of a program voltage increasing in magnitude by a program step amount to selected ones of the plurality of word lines while applying at least one pass voltage to unselected ones of the plurality of word lines during a plurality of programming loops of a programming operation. The control means is also configured to adjust the at least one pass voltage based on the program voltage.

Abstract: Technology is disclosed herein for detecting evolved bad blocks in three-dimensional NAND. The test may include a drain side erase that includes applying an erase voltage from the bit lines and a source side erase that includes applying an erase voltage from the source line(s). If the source side erase performed worse than the drain side erase this may indicate a defect near the source side of the block. For example, the source side erase may fail but the drain side erase may pass. As another example the source side erase may take at least a pre-determined number of additional erase pulses to pass than the drain side erase. If the block is found as having a defect the entire block could be marked bad or the defective region could be identified such that the defective region is no longer used.

Abstract: A memory device includes a memory block including a plurality of sub-blocks each including a plurality of memory cells and control circuitry configured to perform single-side erase operations on the memory block in a sub-block mode in which a selected sub-block of the plurality of sub-blocks in the memory block is erased while unselected sub-blocks of the plurality of sub-blocks in the memory block are not erased and selectively perform data scrubbing and relocation operations on the plurality of sub-blocks of the memory block. To perform a data scrubbing and relocation operation, the control circuitry is configured to determine whether to perform the data scrubbing and relocation operation on a first sub-block based on a position of the first sub-block relative to an erase side of the memory block and selectively perform the data scrubbing and relocation operation on the first sub-block in response to the determination.

Abstract: In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory cells are disposed in memory holes grouped in blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed during at least one read operation. The control means adjusts at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the plurality of data states in the at least one read operation.

Abstract: An apparatus comprising a set of memory cells and a control circuit coupled to the set of memory cells is disclosed. The control circuit is configured to: transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level; subsequent to transitioning the wordline voltage to the second wordline voltage level, ramp down a bitline voltage of a bitline associated with the target memory cell from a first bitline voltage level to a second bitline voltage level; and prior to sensing a state of the memory cell, ramp up the bitline voltage from the second bitline voltage level to the first bitline voltage level.

Abstract: The memory device includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels. The memory device also includes circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels. During the hole pre-charge operation, the circuitry applies a positive CELSRC pre-charge voltage to a source line of the memory block and applies a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.

Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines, where the plurality of word lines are grouped into a plurality of zones based on a size of a word line switch transistor associated with each word line of the plurality of word lines. The memory device also includes a bitline biasing circuit for providing a negative biasing voltage to a bitline corresponding to a memory cell of the selected word line during programming of the selected word line and the bitline biasing circuit is configured to set a magnitude of the negative biasing voltage based on which zone of the plurality of zones the selected word line is in.

Abstract: The memory device includes sensing circuitry that senses data in the memory cells of a selected word line. If the memory device is in the first operating mode, the sensing circuitry senses the selected word line with a first sensing process that includes applying a first voltage to a source side of at least one NAND string and ramping at least one voltage applied to the memory block to a target voltage over a first duration. If the memory device is in the second operating mode, the sensing circuitry senses the selected word line with a second sensing process that includes applying a second voltage to the source side of at least one NAND string and ramping the at least one voltage applied to the memory block to the target voltage over a second duration that is greater than or equal to the first duration.

Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.

Abstract: The memory device includes a memory block with memory cells that are arranged in word lines, some of which are reconfigurable word lines that are dummy word lines when the memory block is operating in a one bit per cell mode and are data word lines when the memory block is operating in a multiple bits per cell mode. Circuitry is configured to program the memory cells of a selected word line. The circuitry determines if the selected word line is a reconfigurable word line. If the selected word line is not a reconfigurable word line, the circuitry programs the memory cells of the selected word line with a first programming scheme. If the selected word line is a reconfigurable word line, the circuitry programs the memory cells of the selected word line with a second programming scheme that is different than the first programming scheme.

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

Abstract: Technology is disclosed herein for a storage system and method for multi-stage discharge of a read pass voltage. In an aspect, the voltage on unselected word lines is reduced from the read pass voltage to an intermediate voltage during a first stage near the end of a read operation. A read reference voltage on the selected word line may be changed (e.g., increased) to the intermediate voltage during the first stage. During a second stage the voltage on the unselected word lines may be reduced from the intermediate voltage to a final voltage. The voltage on the selected word line may also be decreased during the second stage from the intermediate voltage to the final voltage. The multi-stage discharge of the read pass voltage may reduce peak current consumption (e.g., peak Icc) in a final portion of the read operation.

Abstract: Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. If erase does not pass after a number of erase loops, the storage system applies a program pulse to memory cells on faster to erase NAND strings. However, memory cells on slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. The process may continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.

Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.

Abstract: The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.