Abstract: The memory device includes a memory block with an array of memory cells that are arranged word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. During programming, the circuitry is configured to, in a program loop, apply a programming pulse at a programming voltage VPGM to a selected word line to program a plurality of the memory cells of the selected word line to a target data state. The circuitry is also configured to suspend the programming operation for a suspension duration and then resume the programming operation. Before a next program loop, the circuitry is further configured to increase a programming voltage VPGM by a step size that is determined based on the suspension duration and on the targeted data state.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells form a block including an unselected sub-block for an erase operation and a selected sub-block for the erase operation. A control means is configured to identify ones of the word lines of the unselected sub-block that are programmed. The control means applies a selected erase enable voltage to ones of the word lines of the selected sub-block while applying an unselected erase enable voltage to ones word lines of the unselected sub-block to erase the memory cells of the selected sub-block during the erase operation. The unselected erase enable voltage is different for ones of the word lines of the unselected sub-block that are programmed than for ones of the word lines of the unselected sub-block that are erased.

Abstract: The memory device includes a plurality of programmed memory blocks containing data and at least one spare memory block that does not contain data. The memory device also includes control circuitry that is configured to perform a plurality of read operations on the programmed memory blocks. Without having reprogrammed the memory cells of any of the plurality of programmed memory blocks, the circuitry is configured to detect a trigger event. In response to detecting the trigger event, the circuitry is configured to relocate data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block so that the at least one spare memory block becomes a programmed memory block and then erase the selected memory block so that the selected memory block becomes a new spare memory block.

Abstract: To increase the speed of programming, a non-volatile memory system programs some word lines using a two pass programming process and other word lines using a one pass programming process.

Abstract: Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells. To further improve the number of current based data states that can be stored, a ground core structure within the insulating core can introduced along with memory cells with an increased channel length, such as by increasing the relative thickness of the word line layers or shorting together multiple word lines.

Abstract: The memory device includes a memory block with at least one drain-side select gate and an array of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line in a programming operation. In a programming pulse, the circuitry is configured to apply a select gate voltage VSGD to the at least one drain-side select gate, apply a bit line inhibit voltage VDDSA to a plurality of unselected bit lines, apply a very low voltage to a plurality of selected bit lines, and apply a programming voltage to a selected word line of the plurality of word lines. The bit line inhibit voltage VDDSA is no greater than 1.5 V.

Abstract: A memory device is provided that includes a memory block with an array of memory cells that are arranged in word lines, including a selected word line that is programmed according to a storage scheme that has at least three data states. The memory device further includes circuitry for reading the data of the selected word line. During a sensing operation, for a set duration, the circuitry discharges a sensing capacitor through a selected NAND string that includes a selected memory cell to be read. After discharging the sensing capacitor for the set duration, the circuitry conducts a first comparison of a voltage at a sense node to a trip voltage. The circuitry is further applies a first voltage to an opposite side of the sensing capacitor from the sense node and then conducts a second comparison of the voltage at the sense node to the trip voltage.

Abstract: Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells.

Abstract: An apparatus is provided that includes a NAND string including a first memory cell coupled to a first word line, and a control circuit coupled to the NAND string. The control circuit is configured to apply a verify voltage to the first word line, perform a verify test on the first memory cell to sense a hole conduction current, and perform a program operation on the first memory cell without performing a pre-charge operation.

Abstract: The memory device includes a memory block with a source line, a plurality of bit lines, and an array of memory cells that are disposed between the source line and the plurality of bit lines. The memory cells are arranged in a plurality of word lines, which are divided into at least three sub-blocks including a source-side sub-block, a drain-side sub-block, and at least one middle sub-block. The memory device also includes circuitry for programming the memory cells of the memory block. The circuitry is configured to program the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution that includes two data states. The circuitry is also configured to program the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution that is different than the first SLC threshold voltage distribution.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes defining channels. The memory cells form a block including a first sub-block and a second sub-block disposed vertically above the first sub-block. A control means is configured to pre-charge the channels of the memory holes in a pre-charge operation. The control means applies each of a series of programming pulses of a program voltage in a program phase followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines in a verify phase to program and verify the memory cells connected thereto during program loops. The pre-charge operation for the second sub-block occurs during the verify phase of a previously occurring one of the plurality of program loops.

Abstract: A memory apparatus includes memory cells configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to detect whether data stored in a group of the memory cells as one bit per each of the memory cells has errors. The control means is also configured to bypass error correction of the data stored in the group of the memory cells in response to not detecting the errors in the data stored.

Abstract: A non-volatile memory system performs a sensing process for memory cells by sensing the memory cells multiple times to achieve multiple results for determining whether the memory cells are in a particular condition (e.g., a memory cell current distribution) in response to a same reference signal without adjusting the memory cell between the multiple times. The memory system determines whether the memory cells are in the particular condition based on whether a majority of the multiple results indicate that the memory cells are in the particular condition. In one embodiment, the system programs weight information into the non-volatile memory cells and performs vector-matrix multiplication using the weight information programmed in the non-volatile memory cells. The sensing the memory cells multiple times to achieve multiple results can be performed as part of a program verify process when programming weight information and/or as part of the vector-matrix multiplication.

Abstract: A memory apparatus includes memory cells connected to word lines and disposed in memory holes extending vertically through a stack of the word lines. The memory cells form a block including a first sub-block vertically below a second sub-block. A control means is configured to determine a vertical location of a selected one of the word lines connected to the memory cells being programmed in a program operation. The control means applies at least one programming pulse to the selected one of the word lines to program the memory cells connected thereto while applying ones of a plurality of pass voltages to unselected ones of the word lines of the second sub-block during the program operation. The one of the plurality of pass voltages used for each of the unselected ones of the word lines is based on the vertical location of the selected one of the word lines.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines and a plurality of NAND strings. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines to a plurality of data states in a plurality of program loops that include programming pulses and verify operations. During at least one of the verify operations, the circuitry is configured to not lock out a set of the plurality of NAND strings. The NAND strings of the set include at least some of the memory cells of the selected word line that have completed programming so that electricity is conducted through the NAND strings of the set during sensing.

Abstract: A memory apparatus includes memory cells connected to word lines and disposed in memory holes extending vertically through a stack of the plurality of word lines. The memory cells are configured to retain a threshold voltage and form a block including a first sub-block and a second sub-block to define an interface region therebetween. The word lines include dummy word lines disposed adjacent the interface region. A control means is configured to erase the memory cells. The control means is also configured to read the threshold voltage of the memory cells connected to one or more of the dummy word lines and adjust based on the threshold voltage of the memory cells connected to one or more of the dummy word lines relative to a dummy target voltage and based on which of the one of the first sub-block and the second sub-block is erased in the erase operation.

Abstract: A memory apparatus includes memory cells each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to read a subset of the memory cells using only one detect read voltage during a detect read operation prior to a read operation and count a detect bit count of one of the memory cells having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage. The control means is also configured to read the memory cells using at least one adjusted read level for at least one of the plurality of data states during the read operation. The at least one adjusted read level is based on the detect bit count.

Abstract: A method for treating a microsatellite-stable (MSS) solid tumor is provided. The method includes administering a therapeutically effective amount of icariside I to a subject suffering from the MSS solid tumor. The method further includes administering a combination anti-cancer active agent to the subject, the combination anti-cancer active agent includes an immunotherapeutic agent (for example, a PD-1/PD-L1 inhibitor and/or a CAR-T therapy product). A use of the icariside I in the preparation of a drug for treating or preventing the MSS solid tumor, particularly a MSS gastric cancer, a MSS intestinal cancer, a MSS lung cancer, a MSS pancreatic cancer, and a MSS hepatocellular carcinoma, and a kit including the same are further provided. A use of a combination of the icariside I and the immunotherapeutic agent in the preparation of a drug for treating or preventing the MSS solid tumor.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.

Abstract: Technology for programming memory cell transistors to operation region dependent current states. The memory cell transistors may include NAND memory cells. Programming memory cell transistors to a current state may include applying a programming voltage to control gates of the respective memory cells transistor and then verifying the respective memory cells. Verifying may include applying a verify reference voltage to the memory cell transistors and testing their respective currents with respect to a target current state. The same verify reference voltage may be used for all current states. The spacing between the current states depends on whether the memory cell transistor is operating in the sub-threshold region or linear region. The spacing between current states in the linear region may be linear; however, the spacing between current states in the sub-threshold region may be exponential. In-memory compute may be performed using the programmed memory cells.