Abstract: Embodiments disclosed herein are directed to a non-volatile storage system comprising a non-volatile memory including non-volatile storage elements and control circuitry. The control circuitry is configured to: perform a first read operation to access device parameter information for a first memory operation associated with a first storage region type, the device parameter information associated with the first storage region type stored in a first block of a plurality of blocks; perform the first memory operation, using the device parameter information associated with the first storage region type; perform a second read operation to access device parameter information for a second memory operation associated with a second storage region type, the device parameter information associated with the second storage region type stored in a second block of the plurality of blocks; and perform the second memory operation, using the device parameter information associated with the second storage region type.

Abstract: A computer system is provided that includes a single processing unit and a plurality of high bandwidth flash (HBF) packages that are in electrical communication with the single processing unit. Each of the HBF packages has a plurality of memory dies with arrays of memory cells. The HBF packages have a combined bandwidth during read with the single processing unit of at least 2.7 TB/s. The dies have a power efficiency of no greater than 1.1 pJ/bit.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state. The memory device also includes circuitry that is configured to determine that the memory cells have experienced significant of read disturb. Without erasing the memory cells, the circuitry is further configured to program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.

Abstract: A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.

Abstract: Disclosed in the embodiments of the present disclosure are an antenna assembly and a communication terminal, where a base frame is provided with a layout region, and a radiation pattern and a parasitic branch are arranged together on the layout region. Thus, in an aspect, when the communication terminal is assembled, it is convenient to observe the connection between a feed point and a ground point of the antenna assembly, thereby improving the assembly efficiency of the communication terminal. In another aspect, a parasitic branch is arranged near a second branch, so that the antenna has a larger bandwidth in a high frequency band. In yet another aspect, configuring a shape of a first slot, and the parasitic branch enables direct adjustment to a resonance frequency of the antenna, which improves the adaptability of the antenna to different applications.

Abstract: Technology for mixed lockout verify. In a first programming phase, prior to a pre-determined data state completing verification, a no-lockout program verify is performed. After the pre-determined data state has completed verification, a lockout program verify is performed. The no-lockout verify may include charging all bit lines associated with the group to a sensing voltage to perform. The lockout verify may include selectively charging to the sensing voltage only bit lines associated with memory cells in the group to be verified. Bit lines associated with memory cells in the group that are not to be verified may be grounded to perform the lockout verify.

Abstract: The memory device includes a memory block with memory cells arranged in word lines and control circuitry that is configured to program the memory cells in a selected word line to respective programmed data states in program loops, which each include verify operations. The control circuitry is further configured to lock out any of the memory cells in the selected word line memory cell from subsequent program pulses and verify operations in response to that memory cell passing verify for its respective programmed data state. For a selected programmed data state, the control circuitry is further configured to re-verify all of the memory cells in the selected word line that are being programmed to the selected programmed data state and release all memory cells that were locked out but fail re-verify in order to allow any memory cells that mistakenly passed verify to be programmed further.

Abstract: The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

Abstract: The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes coupled to bit lines. A control means successively applies each of a series of pulses of a program voltage to selected ones of the word lines while simultaneously applying one of a bit line program voltage and a bit line inhibit voltage to ones of the bit lines coupled to the memory holes containing groups of the memory cells connected to the selected ones of the plurality of word lines to program the groups of the memory cells with data. The control means maintains a voltage applied to ones of the plurality of bit lines as the bit line inhibit voltage in response to the ones of the plurality of bit lines remaining unselected when programming a next one of the groups of the memory cells.

Abstract: Disclosed in the embodiments of the present disclosure are an antenna assembly and a communication terminal, where a layout region is arranged at an edge position on a base frame, and a radiation pattern and a parasitic branch are arranged together on the layout region. Thus, in an aspect, when the communication terminal is assembled, it is convenient to observe the connection between a feed point and a ground point of the antenna assembly, thereby improving the assembly efficiency of the communication terminal. In another aspect, a parasitic branch is arranged near a second branch, so that the antenna has a larger bandwidth in a high frequency band. In yet another aspect, configuring a shape of a first slot, a second slot, and the parasitic branch enables direct adjustment to a resonance frequency of the antenna, which improves the adaptability of the antenna to different applications.

Abstract: Disclosed in the embodiments of the present disclosure are an antenna assembly and a communication terminal, where a layout region is arranged at an edge position on a base frame, and a radiation pattern and a parasitic branch are arranged together on the layout region. Thus, in an aspect, when the communication terminal is assembled, it is convenient to observe the connection between a feed point and a ground point of the antenna assembly, thereby improving the assembly efficiency of the communication terminal. In another aspect, a parasitic branch is arranged near a second branch, so that the antenna has a larger bandwidth in a high frequency band. In yet another aspect, configuring a shape of a first slot, a second slot, and the parasitic branch enables direct adjustment to a resonance frequency of the antenna, which improves the adaptability of the antenna to different applications.

Abstract: Disclosed in the embodiments of the present disclosure are an antenna assembly and a communication terminal, where a base frame is provided with a layout region, and a radiation pattern and a parasitic branch are arranged together on the layout region. Thus, in an aspect, when the communication terminal is assembled, it is convenient to observe the connection between a feed point and a ground point of the antenna assembly, thereby improving the assembly efficiency of the communication terminal. In another aspect, a parasitic branch is arranged near a second branch, so that the antenna has a larger bandwidth in a high frequency band. In yet another aspect, configuring a shape of a first slot, a second slot, and the parasitic branch enables direct adjustment to a resonance frequency of the antenna, which improves the adaptability of the antenna to different applications.

Abstract: In various aspects, the present disclosure provides polynucleotides encoding a fusion protein, as well as vectors, cells, and compositions comprising the same. In embodiments, the fusion protein includes an insulin signal peptide and an MDA-7/IL-24 protein. Methods of using the polynucleotides, vectors, cells, and compositions, such as in the treatment or prevention of cancer, are also provided.

Abstract: A memory device includes a plurality of memory cells and control circuitry configured to operate in both a quad-level cell (QLC) mode and a triple-level cell (TLC) mode. The control circuity is configured to, to operate in the QLC mode, perform at least one of a QLC programming operation and a QLC read operation on one or more of the plurality of memory cells, to operate in the TLC mode, perform a TLC programming operation on one or more of the plurality of memory cells, and selectively switch between the QLC mode and the TLC mode.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. During programming, the circuitry is configured to, in a program loop, apply a programming pulse at a programming voltage VPGM to a selected word line to program a plurality of the memory cells of the selected word line to a target data state. The circuitry is also configured to suspend the programming operation for a suspension duration and then resume the programming operation. Before a next program loop, the circuitry is further configured to increase a programming voltage VPGM by a step size that is determined based on the suspension duration and on the targeted data state.

Abstract: A memory apparatus includes memory cells connected to word lines and operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is coupled to the word lines and is configured to program the memory cells in a program operation. Following programming of the memory cells connected to specific ones of the word lines, the control means is also configured to apply a predetermined dummy read voltage to the specific ones of the word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the word lines determined based on an amount of the memory cells that are programmed.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes source-side and drain-side select gate transistors for coupling respectively to the source-side and drain-side of memory holes of memory cells. During the read operation, the control means ramps the word lines to a read pass voltage. The control means is configured to delay ramping the voltage applied to the source-side select gate transistors to a select gate voltage until a predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage. The control means is also configured to delay ramping the voltage applied to the drain-side select gate transistors to a select gate voltage until a different predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage.

Abstract: An automotive touch circuit device includes: an analog front-end circuit, a first storage, a second storage, a micro control unit and an ESD protector. The analog front-end circuit has an ESD detector for detection to output a detection result signal. The first storage stores a control parameter having a first error detection code based on which a first error detection signal is generated. The second storage stores touch data having a second error detection code based on which a second error detection signal is generated. The micro control unit generates a notification signal based on the control parameter and touch data. When detecting no ESD interference, the ESD protector enables the notification signal to be output. When detecting ESD interference and an error detection result represented by one of the first and second error detection signals indicates an error, the ESD protector disables the notification signal to be output.

Abstract: Disclosed in the embodiments of the present disclosure are an antenna assembly and a communication terminal, where a layout region is arranged at an edge position on a base frame, and a radiation pattern and a parasitic branch are arranged together on the layout region. Thus, in an aspect, when the communication terminal is assembled, it is convenient to observe the connection between a feed point and a ground point of the antenna assembly, thereby improving the assembly efficiency of the communication terminal. In another aspect, a parasitic branch is arranged near a second branch, so that the antenna has a larger bandwidth in a high frequency band. In yet another aspect, configuring a shape of a first slot, a second slot, and the parasitic branch enables direct adjustment to a resonance frequency of the antenna, which improves the adaptability of the antenna to different applications.