Abstract: Technology for compensation for a sub-block mode (SBM) back pattern effect. When in a sub-block mode, the memory system determines a magnitude for a program verify voltage for a selected word line in a selected sub-block in a selected block. The magnitude for the program verify voltage depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block when the program verify voltage is applied to the selected word line. The memory system may also determine a magnitude for a read reference voltage for the selected word line. The magnitude for the read reference voltage depends on a programmed status of the word lines in the one or more unselected sub-blocks in the selected block when the read reference voltage is applied to the selected word line.

Abstract: To increase endurance of non-volatile semiconductor memory, it is proposed to program N bits of data across M non-volatile memory cells, where M>N, with an encoding scheme that allows for programming M non-volatile memory cells multiple times without performing an intervening erase process.

Abstract: A non-volatile storage apparatus continuously maintains unselected word lines for multiple regions in multiple blocks at one or more overdrive voltages and continuously maintains unselected select lines for multiple regions in multiple blocks at one or more unselected voltages while performing a read process for non-volatile memory cells in one or more regions of one or more blocks of the same die, without lowering those signals to ground or another resting voltage. Selected word lines are separately temporarily toggled to a read reference voltage to enable reading and then reverted back to an overdrive voltage upon completion of the reading. Selected select lines are separately temporarily toggled to a select voltage to enable reading and then reverted back to an unselected voltage upon completion of the reading.

Abstract: A memory device that has a memory block with a plurality of word lines is provided. The memory device also includes circuitry that is configured to read data in a selected word line. The circuitry sets a reference voltage at a reduced voltage that is less than a default voltage and applies the reference voltage to the selected word line and performs a first read operation on the selected word line. In response to the first read operation passing, the circuitry is outputs data to a user. In response to the first read operation not passing, the circuitry sets the reference voltage at the default voltage and applies the reference voltage to the selected word line of the plurality of word lines and performs a second read operation on the selected word line.

Abstract: An apparatus includes a plurality of memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation; and a control circuit connected to the word lines and the bit lines. The control circuit is configured to use, during a setup clock of a loop of a plurality of loops of a program-verify operation, a first verify voltage ramping time period of a plurality of verify voltage ramping time periods based on a data state being verified during the loop, and use, during a setup clock of another loop of a plurality of loops of a program-verify operation, a second verify voltage ramping time period of the plurality of verify voltage ramping time periods based on a data state being verified during the other loop.

Abstract: A system having high bandwidth non-volatile memory, such as NAND. The system senses the combined current of multiple memory cells and then determines a bit value for each cell based on the magnitude of the combined current. The system applies a reference voltage to multiple memory cells with one memory cell per NAND string and then senses a combined current of the multiple memory cells in response to the reference voltage. The system then determines a bit value of each of the multiple memory cells based on a magnitude of the combined current.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state. The memory device also includes circuitry that is configured to determine that the memory cells have experienced significant read disturb. Without erasing the memory cells, the circuitry is further configured to program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. During programming, the circuitry is configured to, in a program loop, apply a programming pulse at a programming voltage VPGM to a selected word line to program a plurality of the memory cells of the selected word line to a target data state. The circuitry is also configured to suspend the programming operation for a suspension duration and then resume the programming operation. Before a next program loop, the circuitry is further configured to increase a programming voltage VPGM by a step size that is determined based on the suspension duration and on the targeted data state.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells form a block including an unselected sub-block for an erase operation and a selected sub-block for the erase operation. A control means is configured to identify ones of the word lines of the unselected sub-block that are programmed. The control means applies a selected erase enable voltage to ones of the word lines of the selected sub-block while applying an unselected erase enable voltage to ones word lines of the unselected sub-block to erase the memory cells of the selected sub-block during the erase operation. The unselected erase enable voltage is different for ones of the word lines of the unselected sub-block that are programmed than for ones of the word lines of the unselected sub-block that are erased.

Abstract: The memory device includes a plurality of programmed memory blocks containing data and at least one spare memory block that does not contain data. The memory device also includes control circuitry that is configured to perform a plurality of read operations on the programmed memory blocks. Without having reprogrammed the memory cells of any of the plurality of programmed memory blocks, the circuitry is configured to detect a trigger event. In response to detecting the trigger event, the circuitry is configured to relocate data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block so that the at least one spare memory block becomes a programmed memory block and then erase the selected memory block so that the selected memory block becomes a new spare memory block.

Abstract: To increase the speed of programming, a non-volatile memory system programs some word lines using a two pass programming process and other word lines using a one pass programming process.

Abstract: Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells. To further improve the number of current based data states that can be stored, a ground core structure within the insulating core can introduced along with memory cells with an increased channel length, such as by increasing the relative thickness of the word line layers or shorting together multiple word lines.

Abstract: The memory device includes a memory block with at least one drain-side select gate and an array of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line in a programming operation. In a programming pulse, the circuitry is configured to apply a select gate voltage VSGD to the at least one drain-side select gate, apply a bit line inhibit voltage VDDSA to a plurality of unselected bit lines, apply a very low voltage to a plurality of selected bit lines, and apply a programming voltage to a selected word line of the plurality of word lines. The bit line inhibit voltage VDDSA is no greater than 1.5 V.

Abstract: A memory device is provided that includes a memory block with an array of memory cells that are arranged in word lines, including a selected word line that is programmed according to a storage scheme that has at least three data states. The memory device further includes circuitry for reading the data of the selected word line. During a sensing operation, for a set duration, the circuitry discharges a sensing capacitor through a selected NAND string that includes a selected memory cell to be read. After discharging the sensing capacitor for the set duration, the circuitry conducts a first comparison of a voltage at a sense node to a trip voltage. The circuitry is further applies a first voltage to an opposite side of the sensing capacitor from the sense node and then conducts a second comparison of the voltage at the sense node to the trip voltage.

Abstract: Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells.

Abstract: An apparatus is provided that includes a NAND string including a first memory cell coupled to a first word line, and a control circuit coupled to the NAND string. The control circuit is configured to apply a verify voltage to the first word line, perform a verify test on the first memory cell to sense a hole conduction current, and perform a program operation on the first memory cell without performing a pre-charge operation.

Abstract: The memory device includes a memory block with a source line, a plurality of bit lines, and an array of memory cells that are disposed between the source line and the plurality of bit lines. The memory cells are arranged in a plurality of word lines, which are divided into at least three sub-blocks including a source-side sub-block, a drain-side sub-block, and at least one middle sub-block. The memory device also includes circuitry for programming the memory cells of the memory block. The circuitry is configured to program the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution that includes two data states. The circuitry is also configured to program the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution that is different than the first SLC threshold voltage distribution.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes defining channels. The memory cells form a block including a first sub-block and a second sub-block disposed vertically above the first sub-block. A control means is configured to pre-charge the channels of the memory holes in a pre-charge operation. The control means applies each of a series of programming pulses of a program voltage in a program phase followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines in a verify phase to program and verify the memory cells connected thereto during program loops. The pre-charge operation for the second sub-block occurs during the verify phase of a previously occurring one of the plurality of program loops.

Abstract: A memory apparatus includes memory cells configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to detect whether data stored in a group of the memory cells as one bit per each of the memory cells has errors. The control means is also configured to bypass error correction of the data stored in the group of the memory cells in response to not detecting the errors in the data stored.

Abstract: A non-volatile memory system performs a sensing process for memory cells by sensing the memory cells multiple times to achieve multiple results for determining whether the memory cells are in a particular condition (e.g., a memory cell current distribution) in response to a same reference signal without adjusting the memory cell between the multiple times. The memory system determines whether the memory cells are in the particular condition based on whether a majority of the multiple results indicate that the memory cells are in the particular condition. In one embodiment, the system programs weight information into the non-volatile memory cells and performs vector-matrix multiplication using the weight information programmed in the non-volatile memory cells. The sensing the memory cells multiple times to achieve multiple results can be performed as part of a program verify process when programming weight information and/or as part of the vector-matrix multiplication.