Patents by Inventor Xiangdong Chen
Xiangdong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12047079Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.Type: GrantFiled: April 18, 2023Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chen Chien, Xiangdong Chen, Hui-Zhong Zhuang, Tzu-Ying Lin, Jerry Chang Jui Kao, Lee-Chung Lu
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Patent number: 12040800Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.Type: GrantFiled: December 13, 2022Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien
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Patent number: 12009824Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.Type: GrantFiled: December 13, 2022Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang, Chi-Lin Liu
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Publication number: 20240097661Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Huaixin XIAN, Tzu-Ying LIN, Liu HAN, Jerry Chang Jui KAO, Qingchao MENG, Xiangdong CHEN
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Publication number: 20240077534Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.Type: ApplicationFiled: January 6, 2023Publication date: March 7, 2024Inventors: Johnny Chiahao Li, Sheng-Hsiung Chen, Tzu-Ying Lin, Yung-Chen Chien, Jerry Chang Jui Kao, Xiangdong Chen
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Publication number: 20240070364Abstract: An integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. The integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. The first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Johnny Chiahao LI, Sheng-Hsiung CHEN, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Xiangdong CHEN, Chung-Hsing WANG
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Patent number: 11870441Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.Type: GrantFiled: December 13, 2022Date of Patent: January 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang, Chi-Lin Liu
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Publication number: 20230421141Abstract: A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.Type: ApplicationFiled: July 6, 2022Publication date: December 28, 2023Inventors: Xing Chao YIN, Huaixin XIAN, Hui-Zhong ZHUANG, Yung-Chen CHIEN, Jerry Chang Jui KAO, Xiangdong CHEN
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Publication number: 20230385504Abstract: A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.Type: ApplicationFiled: August 23, 2022Publication date: November 30, 2023Inventors: Johnny Chiahao LI, Jung-Chan YANG, Jian-Sing LI, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Xiangdong CHEN
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Publication number: 20230387893Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.Type: ApplicationFiled: July 31, 2023Publication date: November 30, 2023Inventors: Seid Hadi RASOULI, Jerry Chang Jui KAO, Xiangdong CHEN, Tzu-Ying LIN, Yung-Chen CHEN, Hui-Zhong ZHUANG, Chi-Lin LIU
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Publication number: 20230275088Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.Type: ApplicationFiled: May 4, 2023Publication date: August 31, 2023Inventors: WEI-LING CHANG, LEE-CHUNG LU, XIANGDONG CHEN, KAM-TOU SIO, HSIANG-CHI HUANG
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Publication number: 20230260786Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Inventors: JOHNNY CHIAHAO LI, SHIH-MING CHANG, KEN-HSIEN HSIEH, CHI-YU LU, YUNG-CHEN CHIEN, HUI-ZHONG ZHUANG, JERRY CHANG JUI KAO, XIANGDONG CHEN
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Publication number: 20230261002Abstract: An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.Type: ApplicationFiled: May 20, 2022Publication date: August 17, 2023Inventors: I-Wen WANG, Chia-Chun WU, Hui-Zhong ZHUANG, Yung-Chen CHIEN, Jerry Chang Jui KAO, Xiangdong CHEN
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Publication number: 20230253406Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Guo-Huei WU, Jerry Chang Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
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Publication number: 20230253961Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Yung-Chen CHIEN, Xiangdong CHEN, Hui-Zhong ZHUANG, Tzu-Ying LIN, Jerry Chang Jui KAO, Lee-Chung LU
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Patent number: 11682671Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.Type: GrantFiled: September 29, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Ling Chang, Lee-Chung Lu, Xiangdong Chen, Kam-Tou Sio, Hsiang-Chi Huang
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Patent number: 11664380Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.Type: GrantFiled: July 12, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guo-Huei Wu, Jerry Chang Jui Kao, Chih-Liang Chen, Hui-Zhong Zhuang, Jung-Chan Yang, Lee-Chung Lu, Xiangdong Chen
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Publication number: 20230131248Abstract: Disclosed herein is a composite material and a skin test platform material in a form of a membrane, comprising silk fibroin and a crosslinking agent, wherein from 4.7 to 14 wt % of the total dry weight of the material is derived from the crosslinking agent. In one embodiment, the crosslinking agent is polyethylene glycol) diglycidyl ether. The membrane has a surface that may be shaped to mimic human skin structures. Also disclosed herein are methods of forming a composite material, a skin test platform material, and determining a property of a test composition such as an anti-bacterial cleansing composition, a skin care product and a perfume.Type: ApplicationFiled: March 11, 2021Publication date: April 27, 2023Inventors: Yajing CUI, Geng CHEN, Xiangdong CHEN, Suxuan GONG
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Patent number: 11632102Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.Type: GrantFiled: June 3, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Yung-Chen Chien, Xiangdong Chen, Hui-Zhong Zhuang, Tzu-Ying Lin, Jerry Chang Jui Kao, Lee-Chung Lu
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Publication number: 20230114367Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien