Abstract: A flip-flop with clock gating based on data comparison is disclosed. The flip-flop unit includes an edge-triggered flip-flop and a clock gating circuit. The clock gating circuit enables or disables a first clock signal to generate a second clock signal according to a data comparison result of input data and output data. The second clock signal provides a triggering edge of the edge-triggered flip-flop. The clock gating circuit copies the first clock signal as the second clock signal in a clock cycle during which the input data is flipped, and maintains the second clock signal at a predetermined level in clock cycles during which the input data remains unchanged. The flip-flop unit enables the clock flip of the edge-triggered flip-flop only in a clock cycle during which the input data is flipped, thereby improving the circuit performance and reducing the power consumption.

Abstract: An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.

Abstract: A scan flip-flop circuit includes first and second I/O nodes, a flip-flop circuit, a selection circuit configured to receive a scan direction signal and including input terminals coupled to the first and second I/O nodes and an output terminal coupled to an input terminal of the flip-flop circuit, and first and second drivers configured to receive the scan direction signal and a scan enable signal, each including an input terminal coupled to an output terminal of the flip-flop circuit and an output terminal coupled to a respective first or second input terminal of the selection circuit. Responsive to the scan direction and scan enable signals, one of the first driver is configured to output a first signal responsive to a second signal received at the second input terminal or the second driver is configured to output a third signal responsive to a fourth signal received at the first input terminal.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A method of manufacturing a semiconductor device includes forming first and second active regions; forming first to fifth gate electrodes, the second gate electrode being between the first and third gate electrodes, the fourth gate electrode being between the third and fifth gate electrodes; and selectively replacing at least one portion of at least one of the gate electrodes with an isolation dummy gate, including: replacing the first and fifth gate electrodes with first and second isolation dummy gates formed in trenches through the first and second active regions; and replacing a first portion of the third gate electrode overlying the second active region with a third isolation dummy gate formed in a first trench through the second active region, resulting in a second portion of the third gate over the first active region, and the third isolation dummy gate aligned with the second portion of the third gate.

Abstract: A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.

Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.

Abstract: A method (of manufacturing) includes forming transistor components connected as transistors resulting in: first to third transistor-component (TC) sets being a primary latch, a secondary latch and a clock buffer that comprise D flip-flop (DFF); the primary latch including a first sleepy inverter and a first non-sleepy (NS) inverter; the secondary latch including a second sleepy inverter and a second NS inverter; the clock buffer including third and fourth NS inverters; a first group of some but not all of the transistors having members with a standard threshold voltage (Vt_std members); a second group of some but not all of the transistors having members with a low threshold voltage; and transistors which comprise at least one of the first NS inverter or the second NS inverter being Vt_low members of the second group.

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor, a first pull-up transistor and an output circuit. The input circuit is coupled to a first and second node, and is configured to receive a first and second enable signal, and to set a first control signal of the first node responsive to the first or second enable signal. The cross-coupled pair of transistors is coupled between the first and second node. The first pull-up transistor includes a first gate terminal configured to receive a clock input signal, a first drain terminal coupled to the second node, and a first source terminal coupled to a voltage supply. The output circuit is coupled between the second node and an output node, and configured to output an output clock signal responsive to the second control signal.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: A method and apparatus for pre-starting a cloud application, a device, a storage medium, and a program product are provided. The method includes: installing a cloud application; in response to determining that the cloud application is provided with a pre-starting switch, pre-starting the cloud application, and rendering a running screen of the cloud application; and sending, in response to receiving a startup instruction of the cloud application sent by a user, the running screen to the user. This implementation provides more cloud application scenarios.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.