Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: Provided are an accurate load shedding system, and a communication method and an access apparatus thereof. The access apparatus includes: two E1 interfaces, eight optical fiber interfaces, a CPU and an FPGA. The two E1 interfaces are respectively connected to a control apparatus A and a control apparatus B of a control substation. The eight optical fiber interfaces are respectively connected to eight control terminals. The FPGA includes eight optical fiber transceivers respectively connected to the eight optical fiber interfaces through serial interfaces, and two E1 transceivers respectively connected to the two E1 interfaces through serial interfaces. Each optical fiber transceiver includes a reset submodule. Each E1 transceiver also includes a reset submodule. The CPU is connected to the FPGA through a parallel bus.

Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

Abstract: Provided are an accurate load shedding system, and a communication method and an access apparatus thereof. The access apparatus includes: two E1 interfaces, eight optical fiber interfaces, a CPU and an FPGA. The two E1 interfaces are respectively connected to a control apparatus A and a control apparatus B of a control substation. The eight optical fiber interfaces are respectively connected to eight control terminals. The FPGA includes eight optical fiber transceivers respectively connected to the eight optical fiber interfaces through serial interfaces, and two E1 transceivers respectively connected to the two E1 interfaces through serial interfaces. Each optical fiber transceiver includes a reset submodule. Each E1 transceiver also includes a reset submodule. The CPU is connected to the FPGA through a parallel bus.

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

Abstract: The present disclosure provides an ultraviolet LED epitaxial production method and an ultraviolet LED, where the method includes: pre-introducing a metal source and a group-V reactant on a substrate, to form a buffer layer through decomposition at a first temperature; growing an N-doped AlwGa1-wN layer on the buffer layer at a second temperature; growing a multi-section LED structure on the N-doped AlwGa1-wN layer at a third temperature, wherein a number of sections of the multi-section LED structure is in a range of 2 to 50; and each section of the LED structure comprises an AlxGa1-xN/AlyGa1-yN multi-quantum well structure and a P-doped AlmGa1-mN layer, and the multi-section LED structure emits light of one or more wavelengths, which realizes that a single ultraviolet LED emits ultraviolet light of different wavelengths, thereby improving the luminous efficiency of the ultraviolet LED.

Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.

Abstract: A method for forming a horizontal overhanging structure without vertical support in selective laser melting, comprising: sequentially forming an initial layer, a repair layer and a conventional layer, wherein initial layer is printed by scanning at a speed set lower than the conventional speed using a laser spot in a defocused state, so that the Plateau-Rayleigh instability effect occurs in each track, to form an initial layer with a specific texture structure; repair layer is printed on upper surface of the initial layer by scanning at a speed set higher than conventional speed in a continuous-wave laser output mode using a laser spot in a focused state, and completes the transition from transition process parameter to conventional process parameters within the set number of processing layers; and conventional layer is printed on upper surface of repair layer using conventional process parameters, to form a horizontal overhanging structure without vertical support.

Abstract: According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

Abstract: According to embodiments of the present invention, devices and methods for requesting information from a target unit and/or for supplying information to a requesting unit are provided. The devices may include one or more modules such as a transmitting module, a processing module, a processor and a memory. A data stream including a request for information may be broadcast. A return data signal may be broadcast including an identifier information based on at least a portion of the data stream, and information corresponding to the request. According to further embodiments of the present invention, there may also be provided applications adapted to be installed on a device, and computer programs and computer program products.

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

Abstract: According to embodiments of the present invention, devices and methods for controlling a target unit, and devices and methods for execution of an instruction in a data stream broadcast by an instructing unit are provided. The devices may include one or more modules such as a processing module, or a processor and a memory. A data stream including an identifying information for verification by the target unit and an instruction to the target unit for controlling the target unit may be broadcast. From the data stream that is received an identifying information included in the data stream may be assessed, and where verified, the instruction included in the data stream may be executed. According to further embodiments of the present invention, there may also be provided applications adapted to be installed on a device, and computer programs and computer program products.

Abstract: In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.

Abstract: Integrated circuits (ICs) employing additional output vertical interconnect access(es) (via(s)) coupled to a circuit output via to decrease circuit output resistance and related methods are disclosed. In exemplary aspects, an output metal interconnect is formed in the IC that extends between a first output contact connected to an output transistor(s) of a circuit, and across an adjacent dummy gate to a second output contact area on the opposite side of the dummy gate from the signal output node. A second output via is connected to the output metal interconnect in the second output contact area. A metal line in a metal layer above the diffusion area and metal contacts is connected to the output via and second output via having parallel output via resistances to reduce the output via resistance of the output transistor(s) of the circuit, and thus reduces the overall resistance of the signal output node of the circuit.