Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Abstract: The present invention discloses an intelligent recognition method for while-drilling safety risks based on a convolutional neural network. The method includes the following steps: 1, processing while-drilling safety risk parameter features and data, and establishing a correlation analysis model for monitoring-while-drilling parameters by using a Pearson coefficient correlation analysis method; 2, processing while-drilling safety monitoring data, analyzing a time span of each sample, constructing training sample data and test sample data, and preprocessing the samples; 3, designing a while-drilling safety risk recognition network structure; and 4, recognizing while-drilling safety risks by the trained safety risk recognition network.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Abstract: A method and apparatus for pre-starting a cloud application, a device, a storage medium, and a program product are provided. The method includes: installing a cloud application; in response to determining that the cloud application is provided with a pre-starting switch, pre-starting the cloud application, and rendering a running screen of the cloud application; and sending, in response to receiving a startup instruction of the cloud application sent by a user, the running screen to the user. This implementation provides more cloud application scenarios.

Abstract: The present disclosure provides an ultraviolet LED epitaxial production method and an ultraviolet LED, where the method includes: pre-introducing a metal source and a group-V reactant on a substrate, to form a buffer layer through decomposition at a first temperature; growing an N-doped AlwGa1-wN layer on the buffer layer at a second temperature; growing a multi-section LED structure on the N-doped AlwGa1-wN layer at a third temperature, wherein a number of sections of the multi-section LED structure is in a range of 2 to 50; and each section of the LED structure comprises an AlxGa1-xN/AlyGa1-yN multi-quantum well structure and a P-doped AlmGa1-mN layer, and the multi-section LED structure emits light of one or more wavelengths, which realizes that a single ultraviolet LED emits ultraviolet light of different wavelengths, thereby improving the luminous efficiency of the ultraviolet LED.

Abstract: A measuring device of Chinese medicine granules includes a dispensing tray, a fixed discharging cover, a discharging driving cover, and a discharging anti-blocking structure mounted coaxially. The dispensing tray, the fixed discharging cover, and the discharging driving cover are provided with storage holes, measuring holes, and discharging holes, respectively. The discharging anti-blocking structure includes a bottom case, a briquetting holder, an anti-blocking briquette, a spring, and a cover. The bottom case is fixed on the dispensing tray and offsets from the storage hole. The bottom case is provided with dispensing holes therein positioned corresponding to the discharging holes. Each of the dispensing holes is provided with one anti-blocking briquette therein. The briquetting holder is connected to the anti-blocking briquette and is disposed in the bottom case. The spring is sleeved on the briquetting holder and is in contact with the cover.

Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

Abstract: An automatic early warning method and system is for a pressure ulcer prone part of a human body. The method includes: constructing a matrix diagram by using marks with variable states; receiving a pressure signal from a pressure sensor matrix laid in an area that a body of a patient is frequently in contact with; corresponding each miniature ultra-thin dynamic pressure sensor contained in the pressure sensor matrix to each mark in the matrix diagram respectively; after receiving a pressure signal indicating that the pressure at a part in contact with the patient, sensed by the pressure sensor matrix, is greater than or equal to a critical value, changing the state of the marks in the matrix diagram, corresponding to the miniature ultra-thin dynamic pressure sensors in the pressure sensor matrix sensing that the pressure is greater than or equal to the critical value, into an early warning state.

Abstract: A method for forming a horizontal overhanging structure without vertical support in selective laser melting, comprising: sequentially forming an initial layer, a repair layer and a conventional layer, wherein initial layer is printed by scanning at a speed set lower than the conventional speed using a laser spot in a defocused state, so that the Plateau-Rayleigh instability effect occurs in each track, to form an initial layer with a specific texture structure; repair layer is printed on upper surface of the initial layer by scanning at a speed set higher than conventional speed in a continuous-wave laser output mode using a laser spot in a focused state, and completes the transition from transition process parameter to conventional process parameters within the set number of processing layers; and conventional layer is printed on upper surface of repair layer using conventional process parameters, to form a horizontal overhanging structure without vertical support.

Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.

Abstract: The present disclosure provides a measuring device of Chinese medicine granules, which includes a dispensing tray, a fixed discharging cover, a discharging driving cover, and a discharging anti-blocking structure mounted coaxially. The dispensing tray, the fixed discharging cover, and the discharging driving cover are provided with storage holes, measuring holes, and discharging holes, respectively. The discharging anti-blocking structure includes a bottom case, a briquetting holder, an anti-blocking briquette, a spring, and a cover. The bottom case is fixed on the dispensing tray and offsets from the storage hole. The bottom case is provided with dispensing holes therein positioned corresponding to the discharging holes. Each of the dispensing holes is provided with one anti-blocking briquette therein. The briquetting holder is connected to the anti-blocking briquette and is disposed in the bottom case. The spring is sleeved on the briquetting holder and is in contact with the cover.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.