Patents by Inventor Xiao Hu Liu
Xiao Hu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7491965Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.Type: GrantFiled: May 28, 2008Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: James P. Doyle, Bruce G. Elmegreen, Lia Krusin-Elbaum, Chung Hon Lam, Xiao Hu Liu, Dennis M. Newns, Christy S. Tyberg
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Publication number: 20080286494Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.Type: ApplicationFiled: March 7, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christos Dimitrios Dimitrakopoulos, Stephen McConnell Gates, Alfred Grill, Michael Wayne Lane, Eric Gerhard Liniger, Xiao Hu Liu, Son Van Nguyen, Deborah Ann Neumayer, Thomas McCarroll Shaw
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INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES
Publication number: 20080277765Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville -
Publication number: 20080251284Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.Type: ApplicationFiled: April 7, 2008Publication date: October 16, 2008Applicant: International Business Machines CorporationInventors: Matthew Earl Colburn, Ricardo Alves Donaton, Conal E. Murray, Satyanarayana Venkata Nitta, Sampath Purushothaman, Sujatha Sankaran, Thedorus Eduardus Fransiscus Maria Standaert, Xiao Hu Liu
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Publication number: 20080224118Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.Type: ApplicationFiled: May 28, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: James P. Doyle, Bruce G. Elmegreen, Lia Krusin-Elbaum, Chung Hon Lam, Xiao Hu Liu, Dennis M. Newns, Christy S. Tyberg
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Publication number: 20080217663Abstract: NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching.Type: ApplicationFiled: March 6, 2007Publication date: September 11, 2008Inventors: Bruce B. Doris, Xiao Hu Liu
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Patent number: 7417315Abstract: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed.Type: GrantFiled: December 5, 2002Date of Patent: August 26, 2008Assignee: International Business Machines CorporationInventors: Gareth Geoffrey Hougham, S. Jay Chey, James Patrick Doyle, Xiao Hu Liu, Christopher V. Jahnes, Paul Alfred Lauro, Nancy C. LaBianca, Michael J. Rooks
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Publication number: 20080179627Abstract: NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Inventors: Meikei Ieong, Xiao Hu Liu, Qiqing Christine Ouyang, Siddhartha Panda, Haizhou Yin
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Publication number: 20080173985Abstract: A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Belyansky, Griselda Bonilla, Xiao Hu Liu, Son Van Nguyen, Thomas M. Shaw, Hosadurga K. Shobha, Daewon Yang
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Patent number: 7394089Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.Type: GrantFiled: August 25, 2006Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: James P. Doyle, Bruce G. Elmegreen, Lia Krusin-Elbaum, Chung Hon Lam, Xiao Hu Liu, Dennis M. Newns, Christy S. Tyberg
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Patent number: 7388273Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: GrantFiled: June 14, 2005Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Geoffrey W. Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen M. Rossnagel, Christy S. Tyberg, Robert L. Wisnieff
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Patent number: 7371684Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.Type: GrantFiled: May 16, 2005Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Matthew Earl Colburn, Ricardo Alves Donaton, Conal E. Murray, Satyanarayana Venkata Nitta, Sampath Purushothaman, Sujatha Sankaran, Theodorus Eduardus Fransiscus Maria Standaert, Xiao Hu Liu
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Patent number: 7357977Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.Type: GrantFiled: January 13, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Christos Dimitrios Dimitrakopoulos, Stephen McConnell Gates, Alfred Grill, Michael Wayne Lane, Eric Gerhard Liniger, Xiao Hu Liu, Son Van Nguyen, Deborah Ann Neumayer, Thomas McCarroll Shaw
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Publication number: 20080048169Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.Type: ApplicationFiled: August 25, 2006Publication date: February 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James P. Doyle, Bruce G. Elmegreen, Lia Krusin-Elbaum, Chung Hon Lam, Xiao Hu Liu, Dennis M. Newns, Christy S. Tyberg
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Publication number: 20070290233Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: ApplicationFiled: August 23, 2007Publication date: December 20, 2007Inventors: Geoffrey Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen Rossnagel, Christy Tyberg, Robert Wisnieff
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Patent number: 7276787Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: GrantFiled: December 5, 2003Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, Paul Stephen Andry, Leena Paivikki Buchwalter, Jon Alfred Casey, Sherif A. Goma, Raymond R. Horton, Gareth Geoffrey Hougham, Michael Wayne Lane, Xiao Hu Liu, Chirag Suryakant Patel, Edmund Juris Sprogis, Michelle Leigh Steen, Brian Richard Sundlof, Cornelia K. Tsang, George Frederick Walker
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Patent number: 7260810Abstract: A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.Type: GrantFiled: October 16, 2003Date of Patent: August 21, 2007Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, Jr., Giovanni Fiorenza, Xiao Hu Liu, Conal Eugene Murray, Gregory Allen Northrop, Thomas M. Shaw, Richard Andre′ Wachnik, Mary Yvonne Lanzerotti Wisniewski
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Patent number: 6972209Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: GrantFiled: November 27, 2002Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Publication number: 20040110322Abstract: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Applicant: International Business Machines CorporationInventors: Gareth Geoffrey Hougham, S. Jay Chey, James Patrick Doyle, Xiao Hu Liu, Christopher V. Jahnes, Paul Alfred Lauro, Nancy C. LaBianca, Michael J. Rooks
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Publication number: 20040101663Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Inventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engel, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw