Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.

Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.

Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.

Abstract: Through-via structures and methods of their formation are disclosed. In one such method, a first etch through at least a first dielectric material of a wiring layer is performed such that a first hole outlining a collar structure for the through-via is formed. In addition, a stress-abating dielectric material is deposited in the hole such that the stress-abating dielectric material is disposed at least laterally from the first dielectric material. Further, a second etching through at least a semiconductor material of a semiconductor layer that is disposed below the wiring layer is performed, where the second etching forms a via hole in the semiconductor material. Additionally, at least a portion of the via hole is filled with conductive material to form the through-via such that the stress-abating dielectric material, at least in the wiring layer, provides a buffer between the conductive material and the first dielectric material.

Abstract: Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining.

Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.