Abstract: In some examples, a semiconductor package comprises an electrically conductive surface and a bond wire coupled to the electrically conductive surface. The bond wire includes a first stitch bond coupled to the electrically conductive surface, and a second stitch bond contiguous with the first stitch bond and coupled to the electrically conductive surface. The second stitch bond is partially, but not completely, overlapping with the first stitch bond.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

Abstract: Method for forming a capacitor includes following operations. A base is provided. First supporting layer and first sacrificial layer are formed on the base sequentially. First through holes penetrating first supporting layer and first sacrificial layer are formed to expose the base. First through holes are filled to form first filling structures. Second supporting layer covering remaining first sacrificial layer and first filling structures is formed. Second through holes penetrating second supporting layer are formed. Second sacrificial layer covering remaining second supporting layer and second through holes, and third supporting layer are formed. Third through holes penetrating third supporting layer and second sacrificial layer are formed. First filling structures are removed to communicate each of third through holes and corresponding one of first through holes.

Abstract: The invention discloses a hydrophilic anti-fog nano paint for endoscope, which includes the following according to the number of weight parts: plant polyphenols of 1-10 parts, metal ions of 0.1-2 parts, biomass molecules of 0.1-0.5 parts, additives of 10-20 parts and solvents of 250 parts; the paint is coated on the surface of the substrate, and the desired coating can be obtained after drying; the plant polyphenol and metal ions in the invention combine to form the plant polyphenol-metal nano complex, form hydrophilic nano-film with biomass molecules on the surface of the laparoscope, and cooperatively enhance the surface interface hydrophilicity of the lens; the formula of the invention has good biocompatibility, will not cause clinical side effects when it comes into contact with tissues, and can meet the needs of clinical use.

Abstract: A memory cell includes a transistor, a storage node contact and a capacitor that are connected sequentially, wherein the capacitor includes a lower electrode, an upper electrode and a dielectric layer disposed between the lower electrode and the upper electrode. The lower electrode includes: a first electrode layer having a first sub-electrode region and a plurality of second sub-electrode regions connected to the first sub-electrode region, where the first sub-electrode region is in contact with a surface of the storage node contact, each of the second sub-electrode regions extends along a direction away from the storage node contact and has a first end face and a second end face facing each other in an extension direction, the first end face being in contact with the surface of the storage node contact; and a second electrode layer, covering at least part of a surface of the first electrode layer.

Abstract: A method for forming a capacitor includes: providing a substrate; sequentially forming a first sacrificial layer and a first support layer for covering the substrate; forming first openings penetrating through the first support layer; sequentially forming a second sacrificial layer and a second support layer for covering a remaining portion of the first support layer; forming through holes which sequentially penetrate through the second support layer, the second sacrificial layer, the remaining portion of the first support layer, and the first sacrificial layer; forming first electrode layers, each first electrode layer covering an inner wall of a respective one of the through holes; forming second openings penetrating through a remaining portion of the second support layer; and sequentially forming a dielectric layer and a second electrode layer for covering the first electrode layers, to form the capacitor.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base and forming, on the base, a bit line contact region provided with a first groove; forming a first bit line contact layer in the first groove, wherein the first bit line contact layer in the first groove defines a second groove; forming a diffusion layer in the second groove, wherein the diffusion layer in the second groove defines a third groove; forming, in the third groove, a second bit line contact layer provided with a gap; and processing the diffusion layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming active pillars arranged in an array on the substrate, a projection shape of a longitudinal section of each of the active pillars includes a cross shape; forming a first oxide layer on the substrate, where a filling region is formed between adjacent active pillars in the same row; sequentially forming a word line and a dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the active pillars; and forming a capacitor structure on the contact layer.

Abstract: A method for forming a thin film by a deposition process, including: a substrate is placed in a deposition chamber; a precursor is introduced into the deposition chamber to form an adsorption layer on a surface of the substrate; a reactant is introduced into the deposition chamber and reacts with the adsorption layer to form a thin film layer on the surface of the substrate and generate reaction byproducts; a vacuuming operation is performed on the deposition chamber to decrease a chamber pressure therein to reduce desorption energy of the reaction byproducts formed at the surface of the thin film layer; plasma is introduced into the deposition chamber to increase energy of the surface of the formed thin film layer; a cleaning gas is introduced into the deposition chamber to discharge the reaction byproducts and the residual precursor and reactant in the deposition chamber.

Abstract: Disclosed in the present disclosure are crystal forms of a fused ring compound, and a composition thereof, a preparation method therefor and use thereof. The crystal forms comprise a crystal form I, a crystal form II, a crystal form III, a crystal form IV and a crystal form V, which have, when using X-ray diffraction, characteristic diffraction peaks at about 11.3 degrees, 17.2 degrees and 21.1 degrees, at about 25.1 degrees, 21.2 degrees and 14.1 degrees, or at about 6.6 degrees, 13.4 degrees and 8.0 degrees, at about 11.8 degrees, 13.3 degrees and 16.7 degrees, and at about 6.5 degrees, 13.3 degrees and 20.0 degrees. The crystal form I or IV is obtained by dissolving a fused ring compound in a proper solvent, followed by stirring, filtering and drying. The use of crystal form I or crystal form IV in preparation of anti-cancer drugs for inhibiting phosphatidylinositol 3-kinase. The use thereof for targeted therapy for tumors, and for anti-inflammation or treatment of autoimmune diseases.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate; etching the substrate to form multiple active areas, trenches each positioned between adjacent active areas, and air gaps positioned below the active areas; and forming a filler layer filling at least each of the trenches.

Abstract: A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a mask pod and a semiconductor device. The mask pod includes: a body, wherein the body has an accommodation space configured to accommodate a mask, the accommodation space has a first opening, and the first opening is located on a circumferential side of the body; and a shielding member, wherein the shielding member is provided on the body and is movably provided relative to the body, to shield or release the first opening.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided; the substrate is etched to form a blind hole, a sidewall of the blind hole has a first roughness; at least one planarization process is performed on the sidewall of the blind hole until the sidewall of the blind hole has a preset roughness less than the first roughness. The planarization process includes: a first sacrificial layer is formed on the sidewall of the blind hole; a reaction source gas is provided such that the reaction source gas reacts with the first sacrificial layer and a portion of the substrate at the sidewall of the blind hole to form a second sacrificial layer; and the second sacrificial layer is removed, and after the second sacrificial layer is removed, the sidewall of the blind hole has a second roughness less than the first roughness.

Abstract: A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.

Abstract: A semiconductor structure includes: a substrate; a through silicon via structure that is located in the substrate; a first heat dissipation layer that is around a side wall of the through silicon via structure, and a material of which is a metal semiconductor compound; and a second heat dissipation layer that is around the side wall of the through silicon via structure and located between the first heat dissipation layer and the through silicon via structure, and a heat conductivity of which is greater than a heat conductivity of the first heat dissipation layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple initial active pillars on the substrate; forming a gate layer between initial active pillars; and forming a first dielectric layer with openings on the gate layer and on the initial active pillars; removing part of the initial active pillar located in each opening to form an active pillar; and removing part of the gate layer to form an isolation trench and a word line, such that two adjacent active pillars in the same row are located on two sides of the isolation trench.

Abstract: The present application discloses a thin-film deposition method and a semiconductor device. The thin-film deposition method in the present application includes: providing a substrate; performing thin-film deposition on the substrate by using a thin-film deposition technology to form a first deposited layer; introducing a purge gas to perform impurity purge treatment on the first deposited layer to form a purified deposited layer; and forming a thin-film layer by the purified deposited layer. In the thin-film deposition method of the present application, the thin-film deposition technology is adopted to form the deposited layer, and impurity purge treatment is performed on the deposited layer.

Abstract: The present invention relates to a composition having an anti-glycation effect and an application thereof. The anti-glycation composition includes the following constituents in parts by mass: 0.1 to 5 parts of Osmanthus fragrans extract, 0.1 to 5 parts of Punica granatum extract and 0.1 to 2 part of Olea europaea extract, wherein in the Osmanthus fragrans extract, a mass content of polyphenol is more than or equal to 10%, and a mass content of verbascoside is more than or equal to 10%; in the Punica granatum extract, a mass content of polyphenol is more than or equal to 30%, and a mass content of punicalagin is more than or equal to 8%; and in the Olea europaea extract, a mass content of polyphenol is more than or equal to 10%, and a mass content of hydroxytyrosol is more than or equal to 3%.