Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

Abstract: A method for forming a thin film by a deposition process, including: a substrate is placed in a deposition chamber; a precursor is introduced into the deposition chamber to form an adsorption layer on a surface of the substrate; a reactant is introduced into the deposition chamber and reacts with the adsorption layer to form a thin film layer on the surface of the substrate and generate reaction byproducts; a vacuuming operation is performed on the deposition chamber to decrease a chamber pressure therein to reduce desorption energy of the reaction byproducts formed at the surface of the thin film layer; plasma is introduced into the deposition chamber to increase energy of the surface of the formed thin film layer; a cleaning gas is introduced into the deposition chamber to discharge the reaction byproducts and the residual precursor and reactant in the deposition chamber.

Abstract: A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.

Abstract: Disclosed in the present disclosure are crystal forms of a fused ring compound, and a composition thereof, a preparation method therefor and use thereof. The crystal forms comprise a crystal form I, a crystal form II, a crystal form III, a crystal form IV and a crystal form V, which have, when using X-ray diffraction, characteristic diffraction peaks at about 11.3 degrees, 17.2 degrees and 21.1 degrees, at about 25.1 degrees, 21.2 degrees and 14.1 degrees, or at about 6.6 degrees, 13.4 degrees and 8.0 degrees, at about 11.8 degrees, 13.3 degrees and 16.7 degrees, and at about 6.5 degrees, 13.3 degrees and 20.0 degrees. The crystal form I or IV is obtained by dissolving a fused ring compound in a proper solvent, followed by stirring, filtering and drying. The use of crystal form I or crystal form IV in preparation of anti-cancer drugs for inhibiting phosphatidylinositol 3-kinase. The use thereof for targeted therapy for tumors, and for anti-inflammation or treatment of autoimmune diseases.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate; etching the substrate to form multiple active areas, trenches each positioned between adjacent active areas, and air gaps positioned below the active areas; and forming a filler layer filling at least each of the trenches.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a mask pod and a semiconductor device. The mask pod includes: a body, wherein the body has an accommodation space configured to accommodate a mask, the accommodation space has a first opening, and the first opening is located on a circumferential side of the body; and a shielding member, wherein the shielding member is provided on the body and is movably provided relative to the body, to shield or release the first opening.

Abstract: A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided; the substrate is etched to form a blind hole, a sidewall of the blind hole has a first roughness; at least one planarization process is performed on the sidewall of the blind hole until the sidewall of the blind hole has a preset roughness less than the first roughness. The planarization process includes: a first sacrificial layer is formed on the sidewall of the blind hole; a reaction source gas is provided such that the reaction source gas reacts with the first sacrificial layer and a portion of the substrate at the sidewall of the blind hole to form a second sacrificial layer; and the second sacrificial layer is removed, and after the second sacrificial layer is removed, the sidewall of the blind hole has a second roughness less than the first roughness.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple initial active pillars on the substrate; forming a gate layer between initial active pillars; and forming a first dielectric layer with openings on the gate layer and on the initial active pillars; removing part of the initial active pillar located in each opening to form an active pillar; and removing part of the gate layer to form an isolation trench and a word line, such that two adjacent active pillars in the same row are located on two sides of the isolation trench.

Abstract: A semiconductor structure includes: a substrate; a through silicon via structure that is located in the substrate; a first heat dissipation layer that is around a side wall of the through silicon via structure, and a material of which is a metal semiconductor compound; and a second heat dissipation layer that is around the side wall of the through silicon via structure and located between the first heat dissipation layer and the through silicon via structure, and a heat conductivity of which is greater than a heat conductivity of the first heat dissipation layer.

Abstract: The present application discloses a thin-film deposition method and a semiconductor device. The thin-film deposition method in the present application includes: providing a substrate; performing thin-film deposition on the substrate by using a thin-film deposition technology to form a first deposited layer; introducing a purge gas to perform impurity purge treatment on the first deposited layer to form a purified deposited layer; and forming a thin-film layer by the purified deposited layer. In the thin-film deposition method of the present application, the thin-film deposition technology is adopted to form the deposited layer, and impurity purge treatment is performed on the deposited layer.

Abstract: The present invention relates to a composition having an anti-glycation effect and an application thereof. The anti-glycation composition includes the following constituents in parts by mass: 0.1 to 5 parts of Osmanthus fragrans extract, 0.1 to 5 parts of Punica granatum extract and 0.1 to 2 part of Olea europaea extract, wherein in the Osmanthus fragrans extract, a mass content of polyphenol is more than or equal to 10%, and a mass content of verbascoside is more than or equal to 10%; in the Punica granatum extract, a mass content of polyphenol is more than or equal to 30%, and a mass content of punicalagin is more than or equal to 8%; and in the Olea europaea extract, a mass content of polyphenol is more than or equal to 10%, and a mass content of hydroxytyrosol is more than or equal to 3%.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, the base including a substrate and a first heat dissipation structure located in the substrate, heat conductivity of the first heat dissipation structure being higher than that of the substrate, the substrate including an upper surface and a lower surface opposite to each other, and a surface of the first heat dissipation structure being exposed on the upper surface of the substrate; a second heat dissipation structure, the second heat dissipation structure being at least located on an upper surface of the first heat dissipation structure; and a through silicon via (TSV) structure, the TSV structure penetrating through an entire thickness of the second heat dissipation structure and extending into the base, the second heat dissipation structure surrounding the TSV structure, and the first heat dissipation structure surrounding the TSV structure.

Abstract: The present disclosure relates to a semiconductor structure and a method for manufacturing a semiconductor structure. The method includes: providing a substrate, interlayer dielectric layer and conductive structures located in the interlayer dielectric layer being formed on the substrate; forming a first isolation dielectric layer on the interlayer dielectric layer and the conductive structures; forming trenches in the first isolation dielectric layer, the trenches exposing upper surfaces and parts of side walls of the conductive structures; and filling in the trenches to form conductive layer structure; and the distance between a bottom side wall of each trench and an exposed side wall of each conductive structure is a first preset value, and the distance between the bottom of each trench and the upper surface of each conductive structure is a second preset value.

Abstract: A resource allocation method and apparatus for flight cabin seats. The method includes: acquiring preset startup information and passenger name record PNR information of a target flight; determining a target flight segment according to a preset flight segment priority; comparing sold cabin seat information with saleable cabin seat information of the changed aircraft type, to determine an overflow state of the target flight segment; if the target flight segment is in a state where a flight is not overloaded and a cabin is overloaded, determining overflowed passengers according to a single-cabin overflowed people quantity and a passenger check-in state of an overloaded main cabin; and allocating target cabin seats to the overflowed passengers according to a preset cabin seat mapping rule.

Abstract: A tracing-based passenger protection method and apparatus, and a check-in system. The method and the apparatus specifically relate to: determining, according to message information included in a received message, whether tracing-based protection is required; when it is determined that tracing-based protection is required, further determining whether a passenger has been subjected to class upgrade or downgrade; and if the passenger has been subjected to class downgrade or upgrade, outputting tracing-based protection scheme information, wherein the tracing-based protection scheme information comprises class upgrade tracing-based protection scheme information of a passenger who has been subjected to class downgrade and class downgrade tracing-based protection scheme information of a passenger who has been subjected to class upgrade.

Abstract: The present invention relates to a process for producing an esterquat by a transesterification reaction of a fatty acid oil or a mixture comprising one or more fatty acid oils and one or more fatty acids with a tertiary hydroxy amine and then a quaternization reaction. Esterquats obtained by the method of the invention show beneficial properties in particular when used as active component in fabric softener materials.

Abstract: Techniques and devices for filtering dialysis fluids, such as dialysis effluent, are described. For example, a filter device may be configured to filter peritoneal dialysis (PD) effluent draining from a patient during a PD process. The filter devices may include filters configured to filter materials, such as human cells, microorganisms, and/or other components from PD effluent. For instance, a filter device may be configured to be installed in-line in a drain circuit of a PD system using conventional tubing. The captured materials may be analyzed or otherwise processed to determine health characteristics of a patient and/or to capture stem cells. Other embodiments are described.

Abstract: The present teachings generally include devices, systems, kits, and methods for collecting, storing, and transporting specimens, e.g., in the context of pool testing. For example, the present teachings may include a compound swab featuring a first swab and a second swab, where the first swab can be detached for pool testing and the second swab can be preserved for testing based on results of the pool test. The present teachings may also or instead include a container having a separator structurally configured to separate swabs of a compound swab. Further, the present teachings may include a swab having a suction enhancer to promote the capture of a specimen on a collection tip thereof. The present teachings may also or instead include a receptacle that can house a plurality of swabs and sever at least a portion of the collections tips thereof, e.g., for pool testing.

Abstract: The invention relates to a mixture measuring system to detect and measure the composition of elements and compounds in a mixture. The system is connected to a cloud server, and it has a canister housing structure in which a sample taking cylinder is inserted to measure the capacitance of the mixture. The system comprises a sonar to measure the volume of the mixture in the cylinder, a gyroscope frame structure which supports a gyroscope stabilizer and other modules including a thermoelectric module, a heat dissipation device, a temperature sensor, a humidity sensor and data processing control. The system enables instant and accurate detection of the composition in the mixture.