Abstract: A voltage-adaptive laser driving circuit and a control method thereof. The circuit includes: a switching power supply, a laser, a constant current driving circuit, a current setting circuit, an MCU control circuit, a voltage acquisition circuit and a voltage setting circuit; the switching power supply is connected to the laser and the voltage setting circuit respectively and used for providing electrical energy for the laser and the voltage setting circuit; and the laser is connected to the switching power supply and the constant current driving circuit respectively and used for generating laser light.

Abstract: A stroboscopic stepped illumination defect detection system for appearance defect detection of a product is provided. The system includes an image extraction unit, a brightness adjustment unit, a data processing unit, and a stroboscopic control unit. The image extraction unit is connected to the stroboscopic control unit and used for obtaining stable and clear images in various transmission/reflection visual bright fields/dark fields; and the brightness adjustment unit is connected to the stroboscopic control unit and used for setting various transmission/reflection visual bright fields/dark fields and converting in the various transmission/reflection visual bright fields/dark fields.

Abstract: Disclosed is a secret-key provisioning (SKP) method and device based on an optical line terminal (OLT), which can generate an SKP queue according to key requests received; generate at least one secret-key according to the SKP queue; and store the at least one secret-key in key pools (KPs) of corresponding ONUS. A non-transitory computer-readable storage medium is also disclosed.

Abstract: The present disclosure discloses a saline wastewater treatment system using solar-assisted heat pump. A method of solar thermal collector coupled with a heat pump can treat saline wastewater at low carbon and high efficiency, and industrial salt and fresh water can be obtained by concentration. The system includes a wastewater pretreatment system, a wastewater heating system, and a wastewater evaporation and concentration treatment system. The wastewater pretreatment system is connected to the wastewater heating system; and the wastewater heating system is connected to the wastewater evaporation and concentration treatment system.

Abstract: A method of preparing a flavor composition containing D-allulose includes: (1) weighing D-allulose, mogroside, steviol glycoside and trichlorosucrose in parts by weight, and mixing them evenly to obtain a mixed powder; (2) degassing, compressing, and rolling the mixed powder, and extruding the raw materials into flakes; and (3) crushing and granulating the shaped flakes to obtain the flavor composition. D-allulose is used as the main raw material, and added high-intensity sweeteners as auxiliary raw materials. After the raw materials are mixed evenly, dry granulation is adopted, and the powder is degassed and pre-compressed by using the crystal water in the raw materials, and squeezed by a hydraulic roller to form a bonding force between the various sweetener molecules to form flakes, and the flakes are processed by processes such as crushing and granulating to obtain the flavor composition granules containing D-allulose with the various sweeteners integrated uniformly as a whole.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another; a first staircase structure formed in the tiers; a second staircase structure formed in the tiers adjacent the first staircase structure, respective portions of conductive materials in the tiers forming a part of the first and second staircase structure and a part of respective control gates associated with memory cells; a first trench structure formed in the tiers adjacent the first staircase structure and the second staircase structure, the first trench structure including length in a direction from the first staircase structure to the second staircase structure; and a second trench structure formed in the tiers adjacent the first trench structure, the second trench structure including a length in the direction from the first staircase structure to the second staircase structure.

Abstract: The present invention provides a display panel and manufacturing method thereof, the method including following steps: providing a driving backplane and a light-emitting substrate, and bonding the driving backplane and the light-emitting substrate; patterning the light-emitting substrate to form a pixel array; forming a thin film packaging layer on an outside of the pixel array, the thin film packaging layer completely covering the pixel array; forming quantum dots on top of the thin film packaging layer to form a multi-color display; forming a reflective array between two adjacent quantum dots to avoid optical crosstalk between the pixel arrays. The display panel and the method of the present invention break through the physical limit of the high PPI, high-precision metal mask, which can realize the display of 2000 and higher PPI, and can prevent the optical crosstalk between the pixel arrays.

Abstract: A variety of applications can include apparatus having a memory device structured with a circuit under array (CuA) architecture. A page buffer region in the CuA can be formed with a periphery region that is horizontally adjacent to the page buffer region. Contacts to gates for transistors in the page buffer region can be formed to land only on these gates, separating and electrically isolating the contacts and associated gates from each other in the page buffer region. Contacts to gates for transistors in the periphery region can be formed to land on conductive regions disposed on gates for transistors in the periphery region.

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure.

Abstract: The present disclosure relates to a method and system for constructing a fusion covert channel. A time covert channel is constructed by rearranging data packets of different terminals in the Internet of Things in a manner of carrying secret information, a storage covert channel is constructed by replacing a TCP sequence number field of a data packet with secret information, and a fusion covert channel is constructed by fusing the time covert channel and the storage covert channel. In this way, advantages of the two channels can be complemented, so that covertness of the fusion covert channel is improved and a capacity of the covert channel is increased.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

Abstract: An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Abstract: A multi-feature log anomaly detection method includes steps of: preliminarily processing a log data set to obtain a log entry word group corresponding to all semantics of a log sequence in the log data set, and using the log entry word group as a semantic feature of the log sequence; extracting a type feature, a time feature and a quantity feature of the log sequence, and encoding the semantic feature, the type feature, the time feature and the quantity feature into a log feature vector set of the log sequence; training a BiGRU neural network model with all log feature vector sets to obtain a trained BiGRU neural network mode; and inputting the log data set to be detected into the trained BiGRU neural network model for prediction, and determining whether the log sequence is a normal or abnormal log sequence according to a prediction result.

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.