Abstract: A display substrate, including: a first base substrate, including a display region and a peripheral region surrounding the display region; at least one common voltage line in the display region, each being configured with at least one conductive connection region; a first passivation layer on a side of the common voltage line away from the first base substrate; a common electrode on a side of the first passivation layer away from the first base substrate; a second passivation layer on a side of the common electrode away from the first base substrate; a pixel electrode on a side of the second passivation layer away from the first base substrate; and a first conductive connection electrode in the corresponding conductive connection region and in the same layer as the pixel electrode, where the common electrode is electrically connected to the common voltage line through the first conductive connection electrode.

Abstract: A display substrate, including a plurality of gate lines and a plurality of data lines defining a plurality of pixel regions, where the plurality of pixel regions include a plurality of normal pixel regions and a plurality of redundant pixel regions at a periphery of the normal pixel regions; where each normal pixel region is provided with a first pixel electrode and a first transistor, each redundant pixel region is provided with a second pixel electrode and a second transistor, a gate of the first transistor is connected to a corresponding gate line, a source of the first transistor is connected to a corresponding data line, and a drain of the first transistor is connected to the first pixel electrode; and the second pixel electrode and the second transistor are insulated and spaced apart from each other.

Abstract: Provided is an array substrate. The array substrate includes a substrate, comprising a display region and a peripheral region surrounding the display region, the peripheral region at least including a gate-driver-on-array (GOA) region extending in a first direction; a plurality of thin film transistors, the plurality of thin film transistors being disposed at least in the GOA region; and a plurality of first patterns, wherein the plurality of first patterns are disposed at least on one side of the GOA region, the plurality of first patterns are spaced apart from the GOA region in the first direction, and a plurality of first patterns disposed on a same side of the GOA region are arranged in an array.

Abstract: A display substrate is provided to include: a first base substrate including a sealing region and a display port region, wherein at least one first connection region and at least one second connection region are in the display port region, a first overlapping region is formed between the second and first connection regions; first and second connection terminals in the first and second connection regions, respectively; and a planarization layer including at least one first trench and at least one second trench corresponding to the first and second connection regions therein, respectively; orthographic projections of bottoms of first and second trenches on the first base substrate cover corresponding first and second connection regions, respectively; the planarization layer includes: a first pattern corresponding to the first overlapping region; orthographic projections of the first pattern and its corresponding first overlapping region on the first base substrate overlap with each other.

Abstract: A display panel, a circuit board and a display device are provided. The display panel includes a first pad region including a first pad connected to a first integrated circuit, a second pad region including a second pad electrically connected to a second integrated circuit, a third pad region including third pads electrically connected to a circuit board and a common signal line electrically connected to the common electrode of the sub-pixel. The display panel further includes a first signal line and a second signal line, the first pad is electrically connected to the third pad through the first signal line, the second pad is electrically connected to the third pad through the second signal line; the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board.

Abstract: An array substrate (000) and a display apparatus, relating to the technical field of display. The array substrate (000) comprises: a substrate (100); a pixel electrode layer (200) and a common electrode layer (300) located on the substrate (100); and a plurality of common signal lines (400) located on the substrate (100), wherein the common signal lines (400) are insulated from the pixel electrode layer (200) and electrically connected to the common electrode layer (300), and an orthographic projection of the common signal lines (400) on the substrate (100) and an orthographic projection of the pixel electrode layer (200) on the substrate (100) have an overlapping area.

Abstract: Provided are a display substrate, display panel and display device. The display substrate comprises: a base substrate, comprising a display area and a surrounding area comprising a gluing area; multiple signal lines; multiple fanout lines, connected to multiple signal lines in a one-to-one correspondence manner. The fanout lines comprise: a first fanout line, and a second fanout line located at the side of first fanout line away from the base substrate; at least in the gluing area, the orthographic projection of the second fanout line on the base substrate substantially overlaps that of the first fanout line on the base substrate; in part of the area outside the gluing area, the size of an overlapping area between orthographic projections of the second fanout line and first fanout line on the base substrate in the direction perpendicular to the extension direction of the fanout lines is smaller than a first preset threshold.

Abstract: The provided is a construction method for a flood storage area ecological wetland oriented to multi-target collaborative promotion. The construction method includes: I. carrying out ecological wetland construction on a flood storage area by taking promotion of agricultural production as a goal; II. according to a water purification target of the flood storage area of the ecological wetland and a current pollution condition in the flood storage area, constructing the ecological wetland based on improvement of the water purification target when the flood storage area does not reach the water purification target at present; and III, in order to improve the biodiversity, carrying out the following ecological wetland construction on the flood storage area. In the method, agricultural production, water purification and biodiversity improvement of the flood storage area are comprehensively considered. The method is the most effective way for multi-target collaborative promotion of the flood storage area.

Abstract: The array base plate includes: the plurality of touch units, wherein each of the touch units includes a plurality of sub-pixels arranged in an array; and each of the sub-pixels includes a first electrode; and a plurality of trace units, wherein each of the trace units includes a first electrode line and a second electrode line that at least partially intersect or overlap in a direction perpendicular to the substrate; the first electrode line includes at least one first parallel-connected part, and the second electrode line includes at least one second parallel-connected part; in each of the trace units, the first parallel-connected part of the first electrode line and the second parallel-connected part of the second electrode line are connected in parallel.

Abstract: A display panel and a display device are disclosed. The display panel comprises an array substrate and spacers; the array substrate comprises a first substrate, gate lines, data lines, and multiple sub-pixel units; the first substrate is provided with multiple sub-pixel regions, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions and intersecting the first wiring regions; at least part of each sub-pixel unit is located on a sub-pixel region; the gate lines and the data lines are respectively located on the first wiring regions and the second wiring regions and are electrically connected to the sub-pixel units; the data lines and the gate lines are insulated from each other and intersect each other; each data line is provided with an alignment part.

Abstract: Disclosed are an array substrate, a display panel and a display apparatus. The array substrate includes: at least one pad group located in a bonding area, and the pad group including a plurality of pads arranged sequentially along a second direction; at least one connection line group disposed on the same side of a substrate as a plurality of data lines in the bonding area, and the connection line group including a plurality of connection lines, an end of a connection line being electrically connected to a data line, and other end of the connection line being electrically connected to a pad, and connection lines of a same connection line group being electrically connected to a same pad group. In the connection line group, multiple connection lines located on at least one side of the pad group are arranged in multiple wiring regions along the second direction.

Abstract: Provided are an array substrate and a display apparatus thereof. The array substrate includes a display region and a binding region located at a side of the display region; the binding region includes a first conductive layer disposed on the substrate and a planarization layer disposed at a side of the first conductive layer away from the substrate. The binding region includes a binding zone and a vacancy zone alternately disposed along an edge of the display region, the first conductive layer includes a plurality of binding pins disposed in the binding zone, and the planarization layer is provided with first openings exposing the plurality of binding pins and covering the binding zone and the vacancy zone.

Abstract: A driving circuit, a driving method, a display substrate and a display device are provided. The driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit and an output circuit; the first node control circuit controls the potential of the first node; the second node control circuit controls the potential of the second node; the third node control circuit controls, under the control of the on-off control signal, the first node to be electrically connected to the third node or the first node to be electrically disconnected from the third node; the output circuit controls, under the control of the potential of the second node and the potential of the third node, output of the driving signal through the driving signal terminal.

Abstract: The present invention discloses an SMA wire-driven reusable release mechanism having a self-resetting function. The present invention adopts a structure of two-stage load reduction and one-stage release. First-stage load reduction: a compression rod and a hoop petal, as well as an inclined block and a shell or a sliding block, all cooperate with each other by means of inclined surfaces, which can transfer most of tension load of the compression rod to the shell, leaving only a small part of the load transmitted to a thrust bearing. Second-state load reduction: balls in the thrust bearing are coated with a molybdenum disulfide lubricating coating, which can effectively reduce friction so as to reduce a torque transmitted to a driving shaft. First-stage release: the driving shaft drives a thrust bearing to rotate by a certain angle, causing an upper ring of the thrust bearing to descend to release a certain axial clearance.

Abstract: Provided is a thin film transistor unit. The thin film transistor unit includes a first gate, a first gate insulating layer, a first semiconductor layer and a first source/drain electrode layer that are sequentially arranged on a substrate, wherein the first source/drain electrode layer includes a first source and a first drain that are spaced apart from each other along a first direction; and a floating electrode disposed on a side of the first semiconductor layer away from the first gate insulating layer, wherein in the first direction, an orthographic projection of the floating electrode on the substrate falls between an orthographic projection of the first source on the substrate and an orthographic projection of the first drain on the substrate.

Abstract: A display panel, a circuit board and a display device are provided. The display panel includes a first pad region including a first pad connected to a first integrated circuit, a second pad region including a second pad electrically connected to a second integrated circuit, a third pad region including third pads electrically connected to a circuit board and a common signal line electrically connected to the common electrode of the sub-pixel. The display panel further includes a first signal line and a second signal line, the first pad is electrically connected to the third pad through the first signal line, the second pad is electrically connected to the third pad through the second signal line; the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board.

Abstract: The present invention relates to a touch substrate with a touch control unit including a first touch electrode having a first bus bar extending along a first direction and a first inner electrode extending from the first bus bar, and a second touch electrode having a second bus bar extending along the first direction and a second inner electrode extending from the second bus bar. The first and second bus bars are disposed opposite to each other, the first and second inner electrodes are between the first and second bus bars, alternately and spaced apart from each other in the first direction. Each pair of adjacent first and second inner electrodes constitutes an inner electrode group, within which, at least a portion of the first inner electrode extends toward the second inner electrode, and at least a portion of the second inner electrode extends toward the first inner electrode.

Abstract: The disclosure provides a display panel and a display device, and belongs to the technical field of display. The disclosure provides a display panel including a central display region and a bent display region at an edge of the central display region. The central display region is provided with a plurality of first pixels, and the bent display region is provided with a plurality of second pixels. A number of second pixels in a unit area is greater than a number of first pixels in the unit area. In the display panel, the PPI of the bent display region is higher than that of the central display region, so the number of the second pixels for gray-scale transition in the bent display region is increased, the gray-scale transition in the bent display region is uniform, and the aliasing phenomenon at the edge of the bent display region is improved.

Abstract: A touch display substrate, an integrated circuit chip and a display device are disclosed. The touch display substrate with an active area and a lead area arranged in sequence includes: a plurality of touch lines arranged in the active area; a plurality of touch leads in one-to-one correspondence with the plurality of touch lines; a plurality of touch electrodes arranged in an array in the active area, each of the touch electrodes is coupled to one of the touch lines; at least two of every three adjacent touch electrodes are connected to different multiplexers through coupled touch lines and touch leads.

Abstract: Provided are a display substrate, display panel and display device. The display substrate comprises: a base substrate, comprising a display area and a surrounding area comprising a gluing area; multiple signal lines; multiple fanout lines, connected to multiple signal lines in a one-to-one correspondence manner. The fanout lines comprise: a first fanout line, and a second fanout line located at the side of first fanout line away from the base substrate; at least in the gluing area, the orthographic projection of the second fanout line on the base substrate substantially overlaps that of the first fanout line on the base substrate; in part of the area outside the gluing area, the size of an overlapping area between orthographic projections of the second fanout line and first fanout line on the base substrate in the direction perpendicular to the extension direction of the fanout lines is smaller than a first preset threshold.