Abstract: A device and a method of making the device comprising, a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate. One or more trenches are formed in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top.

Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.

Abstract: Disclosed is a ground wire spacer structure of a connector, comprising two groups of connector monoblocks that are symmetrical and spliced, wherein any group of the connector monoblocks comprise a housing provided with: a plurality of groups of elastic pieces, wherein one end of the elastic piece is connected to a female socket of the connector, and the other end of the elastic piece is connected to a wire group of the connector; a plurality of metal spacers distributed between two adjacent groups of the elastic pieces and used to separate the elastic pieces; and a conductive sheet mounted on the housing, wherein the conductive sheet is abutted against the plurality of spacers, the conductive sheet is connected to a ground wire in the wire group, and the metal spacers and the conductive sheet form a plurality of independent spaces for accommodating the elastic pieces respectively.

Abstract: A multiple gate transistor and method of its manufacture are described. The transistor comprises a common substrate, a source, a drain, a body, a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are colinearly aligned along a horizontal plane of the common substrate and are separated by a dielectric wall. The dielectric wall provides electrical isolation between the first gate electrode and the second gate electrode.

Abstract: The utility model discloses a small-sized connector convenient for dismounting and mounting, the connector being inserted and received in a female socket of a PCB board, comprising: a connector housing inserted and received in the female socket; two elastic clamping plates, wherein the two elastic clamping plates are symmetrically mounted on both sides of the connector housing, first ends of the two elastic clamping plates are each provided with a clamping hole, and the female socket is provided with a clamping boss clamped with the clamping hole; and a pull strap, wherein both ends of the pull strap are respectively connected to second ends of the two elastic clamping plates, and the pull strap is used to pull the second ends of the two elastic clamping plates to separate the clamping holes at the first ends of the two elastic clamping plates from the clamping bosses of the female socket.

Abstract: A trench MOSFET device implements a trench source/body contact structure and includes a first MOSFET section and a second MOSFET section where the first MOSFET section has a body contact resistance lower than a body contact resistance of the second MOSFET section. In some embodiments, the first MOSFET section includes trench source/body contacts to make electrical contact with the source region and with a body contact doped region having a first doping level. In one embodiment, the second MOSFET section includes trench source/body contacts that contacts only the source region. In another embodiment, the second MOSFET section includes trench source/body contacts to make electrical contact with the source region and with a second body contact doped region having a second doping level lower than the first doping level. In some embodiments, the first MOSFET section has a transistor area much smaller than the transistor area of the second MOSFET section.

Abstract: The present utility model discloses a connector for preventing signal interference, comprising: a connector housing; a plurality of groups of wires arranged in the connector housing, wherein any group of the wires comprise a signal wire and a ground wire, and the ground wires in the plurality of groups of the wires are connected in series; and a metal partition plate, wherein a plurality of spacers are arranged on the metal partition plate, the spacers are positioned on both sides of the wires to separate two adjacent groups of the wires, and the spacers are connected to the ground wires. The present utility model solves the problem of signal interference caused by the absence of an isolation structure between wires in the existing connector.

Abstract: A high-impedance fault positioning method and system based on synchronous Lissajous curve characteristics are provided. The method includes: acquiring a bus zero-sequence differential voltage and a feeder zero-sequence current of a faulty line; constructing a first Lissajous curve in a characteristic frequency band range based on the bus zero-sequence differential voltage and the feeder zero-sequence current; when the proportion of the faulty line is less than a set threshold value and the slope of the first Lissajous curve is negative, determining that high-impedance faults have occurred in the faulty line; constructing a second Lissajous curve based on the bus zero-sequence differential voltage and the section zero-sequence current, performing linear fitting on discrete data points of the second Lissajous curve to obtain a fitted curve; and when the slope of the fitted curve is negative for at least three consecutive periods, determining that high-impedance faults have occurred in the section.

Abstract: A charging structure configured to charge a food thermometer is provided. The charging structure includes a housing, a first electrode component, a second electrode component, and an energy storage element. The housing includes a storage groove for storing the food thermometer. The first electrode component and the second electrode component are disposed on opposite ends of the storage groove, and the first electrode component and the second electrode component are configured to abut against a third electrode and a fourth electrode that are disposed on opposite ends of the food thermometer, respectively. The energy storage element is disposed inside the housing and is electrically connected to the first electrode component and the second electrode component.

Abstract: A method and device for temperature monitoring of a power transistor formed in a semiconductor die comprising are disclosed. A side of a temperature-sensing resistor disposed in the semiconductor die is coupled to a voltage input side of the power transistor. A controller coupled to a second side of the temperature-sensing resistor is configured to detect a voltage across the resistor and trigger a temperature related corrective action using the detected voltage.

Abstract: The present invention provides a system for recovering protein in a production process of an ultrahigh maltose syrup, including a saccharification tank, an enzyme preparation tank, a first plate heat exchanger, a second plate heat exchanger, a plate and frame filter, a buffer tank and a rotary drum filter. The present invention further provides a method of recovering protein by using the system. After the sugar liquid in the saccharification tank is stood, the protein floats at the upper part of the saccharification tank and the lower liquid is clear and transparent and thus the sugar liquid can be directly filtered. When the saccharification tank is discharged, the lower liquid is firstly discharged with the remaining liquid being bottoms containing protein. During a production process, enzymatic hydrolysis is performed for the sugar liquid containing protein before filtration to improve the filtration effect of the sugar liquid. Assisted by the plate and frame filter, protein can be recovered.

Abstract: A device and a method of making the device comprising, a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate. One or more trenches are formed in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top.

Abstract: A method and device for temperature monitoring of a power transistor formed in a semiconductor die comprising are disclosed. A side of a temperature-sensing resistor disposed in the semiconductor die is coupled to a voltage input side of the power transistor. A controller coupled to a second side of the temperature-sensing resistor is configured to detect a voltage across the resistor and trigger a temperature related corrective action using the detected voltage.

Abstract: Embodiments herein relate to systems and methods for detecting aeration properties in fluids using a vibration sensor. In an embodiment, a system for fluid aeration monitoring is included having a vibration sensor configured to be mounted along a fluid flow path, and a control circuit in signal communication with the vibration sensor. The control circuit can be configured to evaluate a signal received from the vibration sensor and calculate one or more aeration parameters based on signals from the vibration sensor. Other embodiments are also included herein.

Abstract: Embodiments herein relate to monitoring systems that can learn patterns of filtration system operation and then use the learned patterns to monitor ongoing filtration system operation/performance. In a first aspect, a monitoring system for an air filtration system is included having a control circuit, and a pressure sensor, wherein the pressure sensor is in electronic communication with the control circuit. The monitoring system can be configured to store data reflecting signals of the pressure sensor, evaluate the stored data representing a first time period to derive a valve operating pattern, and compare data from the pressure sensor obtained after the first time period against the derived valve operating pattern to identify an abnormal valve event.

Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.

Abstract: A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth.

Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.