Abstract: Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.

Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Abstract: A method for checking sets of components of a vehicle includes configuring a system control unit of a vehicle to perform a check of a first set of components and a second set of components of the vehicle, the first set of components being different from the second set of components. The first set of components is automatically checked using the system control unit. The second set of components is optionally checked using the system control unit, wherein the control unit is configured to disable the check of the second set of components based upon a disable command provided to the control system. Further, a system for verifying different sets of components and a further method for checking sets of components of a vehicle are described.

Abstract: A method for making a book is provided in the embodiments of the present invention. The method mainly comprises: cutting printed sheets for a book, brushing glue onto edges of the printed sheets, bonding the printed sheets through the glue, and positioning and fixing a plurality of bonded printed sheets by utilizing a right-angled mold; perforating each, of the positioned and fixed printed sheets, and stringing holes of the printed sheets so as to reinforce the printed sheets; and splicing front endpaper and rear endpaper onto endpaper connection cloth, and then, bonding the endpaper and bookblocks. The embodiments of the present invention adopt a right-angled mold to position register and fix a plurality of bonded printed sheets, and pages are unlikely to dislocate, thereby guaranteeing the binding quality of the book, improving the attractiveness of the book, reducing a making time of the book, and improving the production efficiency of the book.

Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

Abstract: A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic coercivity Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.

Abstract: The present invention is directed to an MTJ memory element including a magnetic free layer structure which comprises one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure comprising a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated therefrom by a perpendicular enhancement layer with the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the perpendicular enhancement layer; and a magnetic fixed layer comprising first and second magnetic fixed sublayers with the second magnetic fixed sublayer formed adjacent to the anti-ferromagnetic

Abstract: The embodiments of the disclosure provide a method and device for switching channel. The method comprises: when a first touch gesture for a first channel is detected, loading a first channel display window; displaying channel information of the first channel on the first channel display window; according to a detected second touch gesture, moving at least a portion of channel information of the first channel out of and moving at least a portion of channel information of a second channel into the first channel display window; and when the moved-out channel information of the first channel or the moved-in channel information of the second channel satisfies a predefined switching condition, playing back video data of the second channel. The displaying of channel information informs user of the channel which can be triggered by the touch gesture, and the switching of channel information informs user of the timing of channel switch.

Abstract: The embodiments of the present invention provide a method and a device for previewing and displaying multimedia streaming data, wherein the method includes: when a terminal displays a designated interface, determining a thumbnail display area corresponding to at least one previewing and playing area preset in the designated interface, acquiring multimedia streaming data corresponding to the previewing and playing area, loading a floating layer playing control in the previewing and playing area, and previewing and playing the multimedia streaming data.

Abstract: The embodiments of the disclosure provide a method and device for switching channel. Method includes: when a first touch gesture for a first channel is detected, loading at least one channel display window after an enlargement processing; displaying channel information of the first channel on the channel display window of a display interface; when a second touch gesture is detected, moving the channel information displayed on channel display windows based on a direction of the second touch gesture; and when the channel information of the second channel is displayed on the channel display window of the display interface, playing back video data of the second channel. In the embodiments of the disclosure, the displaying of channel information informs user of the channel which can be triggered by the touch gesture, and the switching of channel information informs user of the timing of channel switch.

Abstract: The present invention provides a method and a device for previewing video files. The method includes: receiving a video file previewing instruction; determining a given dynamic previewing area in response to the instruction; acquiring information of a first video file currently mapped by the dynamic previewing area from a source code of an interface to be displayed; and requesting to acquire the first video file from a resource server, and playing the first video file acquired in the dynamic previewing area when displaying the interface to be displayed.

Abstract: The embodiments of the disclosure provide a method and device for video preview. The method includes: with the determination of a need to enter a video preview interface, obtaining a respective preview control corresponding to at least one playback position for playing a preview video in a video preview interface; loading video data of respective one way of preview video corresponding to each of the preview controls; and playing the video data of the respective one way of preview video in each of preview controls. The embodiments of the disclosure can reflect preview video contents accurately in real time, allowing the user to rapidly and accurately find the desirable video, improving the user experience. The video preview manner may have enhanced universality, especially applicable to the preview of the videos having varied contents in real time such as live broadcast and carousel.

Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Abstract: A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.