Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

Abstract: A DRGs automatic grouping method based on convolutional neural network, including: collecting case data and grouping according to a major diagnostic broad categories and core diagnosis-related grouping method; performing numerical coding to the data; constructing a shallow convolutional neural network model, using a k-means clustering method to cluster the feature vectors extracted from the convolutional network to obtain k category labels, combining the category labels and classifier to supervise the network performing iterative training; after finishing training the model, perform data grouping application. The method of the present disclosure is used to avoid the disadvantages of manual feature selection and additional data labeling for adding new grouping categories, automatic learning grouping can be performed for data with vague and difficult groupings.

Abstract: A chronic disease prediction system based on a multi-task learning model. The system includes a computer memory, a computer processor and a computer program which is stored in the computer memory and executable on the computer processor, wherein a trained chronic disease prediction model is stored in the computer memory, and the chronic disease prediction model is composed of a shared layer convolutional neural network and a plurality of chronic disease branch networks; and when executing the computer program, the computer processor implements the following steps: preprocessing a to-be-predicted physical examination record and then inputting the record into the shared layer convolutional neural network of the chronic disease prediction model for feature extraction to obtain a feature map, and inputting the obtained feature map into each chronic disease branch network and performing feature extraction and prediction respectively to obtain a chronic disease prediction result.

Abstract: The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material.

Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a photodiode.

Abstract: A GAA transistor includes a semiconductor substrate. A first shallow trench isolation (STI) is embedded in the semiconductor substrate. A top surface of the first STI is lower than a top surface of the semiconductor substrate. A nanowire crosses the first STI and is disposed on the first STI. A gate structure contacts and wraps around the nanowire. A source electrode contacts a first end of the nanowire. A drain electrode contacts a second end of the nanowire.

Abstract: A method for stabilizing bandgap voltage includes the steps of: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and then outputting the second layout pattern to a mask. Preferably, the first layout pattern and the second layout pattern include polysilicon resistor patterns.

Abstract: A process knowledge system for traditional Chinese medicine production includes a database module having production data acquisition and storage units. The production data acquisition unit acquires process parameter data in production. The parameter data includes quality and process data and is stored in the storage unit. A capability evaluation module evaluates the process capability of the system according to the quality data to obtain a process capability evaluation result. A monitoring feedback module enters a whole-process monitoring mode the process capability is found sufficient. A design space searching module enters a design space searching mode when the process capability is found insufficient.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

Abstract: In one embodiment, an integrated circuit die includes first and second inductor structures, a first ground conductor, a second ground conductor and a conductive trace. The first ground conductor provides a first ground pathway for the first inductor structure. The second ground conductor provides a second ground pathway for the second inductor structure. The conductive trace coupled between the first and second ground conductors may magnetically decouple the first and second inductor structures. In addition, the integrated circuit die may also include conductive guard ring structures that surround the first and second inductor structures. One of the conductive guard ring structures may be connected to the first grounding pathway and the other conductive guard ring structure may be connected to the second grounding pathway. The conductive guard ring structures may further magnetically decouple the first and second inductor structures.

Abstract: In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.

Abstract: In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.

Abstract: An integrated circuit package substrate may include a core layer and dielectric layers formed on top and bottom surfaces of the core layer. Routing traces such as stripline structures may be formed in some of the dielectric layers, whereas plated through hole (PTH) structures may be formed through the core layer. A first pair of PTHs that carry a first differential signal may be orthogonally intertwined with a second pair of PTHs that carry a second differential signal. Solder balls formed at the surface of the package substrate may include a first pair of solder balls that convey a first differential signal that is orthogonally intertwined with respect to a second pair of solder balls that convey a second differential signal. The package substrate may be mounted on a printed circuit board (PCB). Differential PCB vias could use the same BGA orthogonal pattern described above.

Abstract: An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that has dielectric layers and metal layers stacked up alternately. The dielectric layers in the package substrate have different thickness. The metal layers may be ground, signal or power layers. A thicker dielectric layer is placed in between a signal layer and a power layer in the package substrate. The thicker dielectric layer may be at least twice as thick as other dielectric layers in the package substrate. The thicker dielectric layer may provide better impedance control in the package substrate.

Abstract: Integrated circuit packages with stripline structures are provided. An integrated circuit package substrate may include a core layer having top and bottom surfaces and dielectric layers formed on the top and bottom surfaces of the core layer. Stripline structures may be formed in at least some of the dielectric layers. A stripline trace may include signal routing conductors sandwiched between top and bottom ground planes. In particular, a dielectric layer may be formed between the signal conductors and the bottom ground plane to support the signal conductors, whereas a localized air region may be formed over the signal routing conductors separating the signal conductors from the top ground plane. If desired, the region above the signal routing conductors between the top ground plane and the signal routing conductors may be filled using other types of material having low loss and/or a dielectric constant that is frequency independent.

Abstract: An integrated circuit package having a package substrate, an integrated circuit, and at least one solder ball is provided. The package substrate has first and second surfaces. The integrated circuit may be mounted on the first surface of the package substrate. The solder ball may be coupled to the second surface of the package substrate. The package substrate may include a substrate layer. The substrate layer may include a ground plane with an opening. The opening may be formed just above the solder ball. In one instance, the diameter of the opening is greater than the diameter of the solder ball pad.

Abstract: In one embodiment, a printed circuit board (PCB) comprises one or more signal contact pads on a surface of the PCB and a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pads) having gaps in line with the trace(s). In another embodiment, a PCB comprises one or more signal traces on a first surface of the PCB, a plurality of ground planes embedded in the PCB, and at least one blind via interconnecting the ground planes. In still another embodiment, a PCB comprises one or more signal contact pads on a first surface of the PCB, a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pad(s) having a gap in line with the signal contact pad(s), and at least one blind via interconnecting the ground planes. In still another embodiment, signal contact pads may be formed on both major surfaces of the PCB.

Abstract: An integrated circuit with an on-die compensation network is presented. The compensation network includes a compensation inductor that has one terminal coupled to a bump pad of the die. Another terminal of the inductor is connected to a metal layer underneath the compensation inductor, forming a pi-configuration with the bump pad. The metal layer routes input and output signals from the integrated circuit. The invention can be used in either flip chip or wire bond applications.