Abstract: Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.

Abstract: An integrated circuit with an on-die compensation network is presented. The compensation network includes a compensation inductor that has one terminal coupled to a bump pad of the die. Another terminal of the inductor is connected to a metal layer underneath the compensation inductor, forming a pi-configuration with the bump pad. The metal layer routes input and output signals from the integrated circuit. The invention can be used in either flip chip or wire bond applications.

Abstract: In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package.

Abstract: In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package. In the first row, ground contacts alternate with contacts for receiving differential signals and in the second row ground contacts alternate with contacts for transmitting differential signals.

Abstract: Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.

Abstract: Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: An apparatus which aligns a ball grid array (BGA) device over a substrate. The apparatus preferably includes a cup-shaped member for cupping and holding the solder balls of the BGA device, and an elongate member attached to the cup-shaped member. The cup-shaped member is attached between the BGA device and the substrate at two or more different positions so that the solder balls of the BGA device become aligned over the terminals of the substrate by operation of gravity.